Datasheet

PIC18F97J94 FAMILY
DS30575A-page 682  2012 Microchip Technology Inc.
External Clock Input ........................................................... 52
External Memory Bus ....................................................... 153
16-Bit Byte Select Mode ..........................................159
16-Bit Byte Write Mode ............................................157
16-Bit Data Width Modes ......................................... 156
16-Bit Mode Timing .................................................. 160
16-Bit Word Write Mode ........................................... 158
8-Bit Data Width Mode ............................................. 161
8-Bit Mode Timing .................................................... 162
Address and Data Lines for Different Address
and Data Widths (table) ................................... 155
Address and Data Width .......................................... 155
Address Shifting .......................................................155
Control .....................................................................154
I/O Port Functions .................................................... 153
Operation in Power-Managed Modes ...................... 163
Program Memory Modes ......................................... 156
Extended Microcontroller ................................. 156
Microcontroller ................................................. 156
Wait States ............................................................... 156
Weak Pull-ups on Port Pins ..................................... 156
F
Fail-Safe Clock Monitor ............................................ 553, 571
Exiting Operation .....................................................571
Interrupts in Power-Managed Modes ....................... 572
POR or Wake from Sleep ........................................572
WDT During Oscillator Failure ................................. 571
Fail-Safe Clock Monitor (FSCM) ........................................ 57
and WDT .................................................................... 57
Delay ..........................................................................57
Slow Oscillator Start-up ............................................. 57
Family Member Details ......................................................11
Fast Register Stack .......................................................... 117
Firmware Instructions ....................................................... 575
Flash Program Memory .................................................... 143
Control Registers ..................................................... 144
EECON1 and EECON2 ................................... 144
TABLAT (Table Latch) .....................................146
TBLPTR (Table Pointer) .................................. 146
Operations with TBLRD, TBLWT ............. 146
Erase Sequence ...................................................... 148
Erasing ..................................................................... 148
Operation During Code-Protect ............................... 152
Reading .................................................................... 147
Table Pointer Boundaries ........................................ 146
Based on Operation ......................................... 146
Table Reads, Table Writes ...................................... 143
Write Sequence ....................................................... 149
Writing ...................................................................... 149
Unexpected Termination .................................. 152
Write Sequence ............................................... 151
Write Verify ...................................................... 152
FSCM. See Fail-Safe Clock Monitor.
G
Getting Started Guidelines .................................................31
GOTO ...............................................................................596
H
Hardware Multiplier ..........................................................165
8 x 8 Multiplication Algorithms .................................165
Operation ................................................................. 165
Performance Comparison (table) ............................. 165
High/Low-Voltage Detect .................................................501
Applications .............................................................. 505
Current Consumption ............................................... 503
Effects of a Reset .................................................... 505
Operation ................................................................. 502
During Sleep .................................................... 505
Setup ....................................................................... 503
Start-up Time ........................................................... 503
Typical Application ................................................... 505
HLVD. See High/Low-Voltage Detect. ............................. 501
I
I/O Ports ........................................................................... 197
Open-Drain Outputs ................................................. 199
Output Pin Drive ...................................................... 197
Pin Capabilities ........................................................ 197
PPS-Lite .................................................................. 224
Pull-up Configuration ............................................... 197
Virtual PORT ............................................................ 224
I
2
C Mode (MSSP)
Acknowledge Sequence Timing .............................. 404
Baud Rate Generator .............................................. 397
Bus Collision
During a Repeated Start Condition .................. 408
During a Stop Condition .................................. 409
Clock Arbitration ...................................................... 398
Clock Stretching ....................................................... 390
10-Bit Slave Receive Mode (SEN = 1) ............ 390
10-Bit Slave Transmit Mode ............................ 390
7-Bit Slave Receive Mode (SEN = 1) .............. 390
7-Bit Slave Transmit Mode .............................. 390
Clock Synchronization and the CKP bit ................... 391
Effects of a Reset .................................................... 405
General Call Address Support ................................. 394
I
2
C Clock Rate w/BRG ............................................. 397
Master Mode ............................................................ 395
Operation ......................................................... 396
Reception ........................................................ 401
Repeated Start Condition Timing .................... 400
Start Condition Timing ..................................... 399
Transmission ................................................... 401
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 405
Multi-Master Mode ................................................... 405
Operation ................................................................. 380
Read/Write
Bit Information (R/W Bit) ............... 380, 383
Registers ................................................................. 372
Serial Clock (RC3/SCKx/SCLx) ............................... 383
Slave Mode .............................................................. 380
Address Masking Modes
5-Bit ......................................................... 381
7-Bit ......................................................... 382
Addressing ....................................................... 380
Reception ........................................................ 383
Transmission ................................................... 383
Sleep Operation ....................................................... 405
Stop Condition Timing ............................................. 404
ID Locations ..................................................................... 553
INCF ................................................................................ 596
INCFSZ ............................................................................ 597
In-Circuit Debugger .......................................................... 573
In-Circuit Serial Programming (ICSP) ...................... 553, 573
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 622
Indexed Literal Offset Mode ............................................. 622
Indirect Addressing .......................................................... 137
INFSNZ ............................................................................ 597
Initialization Conditions for All Registers .................... 97–112