Datasheet

PIC18F97J94 FAMILY
DS30575A-page 68  2012 Microchip Technology Inc.
4.2.3 IDLE MODE
When the device enters Idle mode, the following events
occur:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source will remain active and
the peripheral modules, by default, will continue to
operate normally from the system clock source.
Peripherals can optionally be shut down in Idle
mode using their ‘Stop in Idle’ control bit. (See
peripheral descriptions for further details.)
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
The processor will wake-up from Idle mode on the
following events:
• On any interrupt that is individually enabled.
• On any source of device Reset.
• On a WDT time-out.
Upon wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution begins immediately,
starting with the instruction following the SLEEP instruc-
tion, or the first instruction in the Interrupt Service
Routine (ISR).
4.2.3.1 Time Delays on Wake-up from Idle
Mode
Unlike a wake-up from Sleep mode, there are no addi-
tional time delays associated with wake-up from Idle
mode. The system clock is running during Idle mode,
therefore, no start-up times are required at wake-up.
4.2.3.2 Wake-up from Idle on Interrupt
Any source of interrupt that is individually enabled
using the corresponding control bit in the PIEx register,
will be able to wake-up the processor from Idle mode.
When the device wakes from Idle mode, one of two
options may occur:
• If the GIE bit is set, the processor will wake and
the Program Counter will begin execution at the
interrupt vector.
• If the GIE bit is not set, the processor will wake
and the Program Counter will continue execution
following the SLEEP instruction.
The PD
status bit (RCON<2>) is set upon wake-up.
4.2.3.3 Wake-up from Idle on Reset
Any Reset, other than a Power-on Reset (POR), will
wake-up the CPU from Idle mode on any device Reset,
except a POR.
4.2.3.4 Wake-up from Idle on WDT Time-out
If the WDT is enabled, then the processor will wake-up
from Idle mode on a WDT time-out and continue code
execution with the instruction following the SLEEP
instruction that initiated Idle mode. Note that the WDT
time-out does not reset the device in this case. The TO
bit (RCON<3>) will be set.
4.2.4 SLEEP MODES
Most PIC18F97J94 family devices that incorporate
power-saving features and V
BAT, offer two distinct
Sleep modes: Sleep mode and Retention Sleep mode.
The characteristics of both Sleep modes are:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption will be optimum,
provided no I/O pin is sourcing the current.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode since the system
clock source is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT is enabled.
• If Brown-out Reset (BOR) is enabled, the
Brown-out Reset (BOR) circuit remains
operational during Sleep mode.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some peripherals may continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal or
peripherals that use an external clock input. Any
peripheral that operates from the system clock
source will be disabled in Sleep mode.
The processor will exit, or ‘wake-up’ from Sleep on one
of the following events:
• On any interrupt source that is individually
enabled
• On any form of device Reset
• On a WDT time-out