Datasheet

 2012 Microchip Technology Inc. DS30575A-page 67
PIC18F97J94 FAMILY
4.2 Instruction-Based Power-Saving
Modes
PIC18F97J94 family devices have 3 instruction-based
power-saving modes; two of these have additional
features that allow for additional tailoring of power
consumption. All three modes are entered through the
execution of the SLEEP instruction. In descending order
of power consumption, they are:
• Idle Mode: The CPU is disabled, but the system
clock source continues to operate. Peripherals
continue to operate, but can optionally be
disabled.
• Sleep Modes: The CPU, system clock source and
any peripherals that operate on the system clock
source are disabled.
• Deep Sleep Modes: The CPU system clock
source, and all the peripherals except RTCC and
DSWDT are disabled. This is the lowest power
mode for the device. The power to RAM and
Flash is also disabled. Deep Sleep modes
represent the lowest power modes available
without removing power from the application.
Idle and Sleep modes are entered directly with the
SLEEP statement. Having IDLEN (OSCCON<7>) set
prior to the SLEEP statement will put the device into Idle
mode. For Deep Sleep mode, it is necessary to set the
DSEN bit (DSCONH<7>). To prevent inadvertent entry
into Deep Sleep mode, and possible loss of data, the
DSEN bit must be written to twice. The write need not
be consecutive instructions; however, it is a better
practice to write both, one after the other. It is also
recommended to clear the DSCON1 register before
setting the DSEN bit (Example 4-1).
EXAMPLE 4-1: SLEEP ASSEMBLY
SYNTAX
The instruction-based power-saving modes are exited
as a result of several different hardware triggers. When
the device exits one of these three operating modes, it
is said to ‘wake-up’. The characteristics of the
power-saving modes are described in the subsequent
sections.
4.2.1 INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
SLEEP instruction will be held off until entry into Sleep,
Idle or Deep Sleep mode is completed. The device will
then wake-up from the power-managed mode.
Interrupts that occur during the Deep Sleep unlock
sequence will interrupt the mandatory unlock sequence
and cause a failure to enter Deep Sleep. For this
reason, it is recommended to disable all interrupts
during the Deep Sleep unlock sequence.
4.2.2 RETENTION REGULATOR
A second on-chip voltage regulator is used for power
management in Sleep and Deep Sleep modes. This
regulator, also known as the retention regulator, sup-
plies core logic and other circuits with power at a lower
V
CORE level, about 1.2V nominal. Running these
circuits at a lower voltage allows for an additional
incremental power saving over the normal minimum
V
CORE level.
In Retention Sleep modes, using the regulator main-
tains the entire data RAM and its contents, instead of
just a few protected registers. This allows the device to
exit a power-saving mode and resume code execution
as its previous state.
The retention regulator is controlled by the Configuration
bit, RETEN
(CONFIG7L<0>), and the SRETEN bit
(RCON4<4>). The RETEN
bit makes the retention
regulator available for software control. By default
(RETEN = 1), the regulator is disabled and the SRETEN
bit has no effect. Programming RETEN
(= 0) allows the
SRETEN bit to control the regulator’s operation, leaving
its use in power-saving modes at the user’s discretion.
Setting the SRETEN bit prior to executing the SLEEP
instruction puts the device into Retention Sleep mode.
If the DSEN bit was also unlocked and set prior to the
instruction, the device will enter Retention Deep Sleep
mode.
The retention regulator is not available outside of
Sleep, Deep Sleep or V
BAT modes. Enabling it while
the device is operating in Run or Idle modes does not
allow the device to operate at a lower level of V
CORE.
Note: SLEEP_MODE and IDLE_MODE are con-
stants defined in the Assembler Include
file for the selected device.
clrf DSCON1
clrf DSCON1
bsf DSCON1,7
bsf DSCON1,7
sleep
or
movlw 0x80
movwf DSCON1
movwf DSCON1
sleep