Datasheet

 2012 Microchip Technology Inc. DS30575A-page 661
PIC18F97J94 FAMILY
FIGURE 31-22: A/D CONVERSION TIMING
TABLE 31-37: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
Sample Start Delay from Setting SAMP 2 3 T
AD
130 TAD A/D Clock Period 300 — ns
250 — ns A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)
(2)
14 15 TAD
132 TACQ Acquisition Time
(3)
— 750 ns -40°C to +85°C
(5)
135 TSWC Switching Time from Convert  Sample — (Note 4)
T
DIS Discharge Time 1 — TAD -40°C to +85°C
A/D Stabilization Time (from setting ADON
to setting SAMP)
300 — ns
Note 1: The time of the A/D clock period is dependent on the device frequency and the T
AD clock divider.
2: ADRES registers may be read on the following T
CY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
DD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
4: On the following cycle of the device clock.
5: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
DD to AVSS or AVSS to AVDD).
131
130
132
BSF ADCON1L, SAMP
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11 10 9 2 1 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the SLEEP instruction to
be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY (Note 1)