Datasheet

PIC18F97J94 FAMILY DS30575A-page 66  2012 Microchip Technology Inc.
TABLE 4-1: SUMMARY OF OPERATING MODES FOR PIC18F97J94 FAMILY DEVICES WITH VBAT POWER-SAVING FEATURES
Mode Entry
Active Systems
Exit Conditions
Interrupts Resets
RTCC Alarm
(DS)WDT
(3)
VDD Restore
Code Execution
Resumes
Core
Peripherals
Data RAM
Retention
RTCC
(1)
DSGPRx
(2)
All
INT0 Only
All
POR
MCLR
Run (default) N/A Y Y Y Y Y N/A N/A N/A N/A N/A N/A N/A N/A N/A
Idle Instruction N Y Y Y Y Y Y Y Y Y Y Y N/A Next Instruction
Sleep modes:
Sleep Instruction N N
(4)
Y Y Y Y Y Y Y Y Y Y N/A Next Instruction
Retention
Sleep
Instruction +
R
ETEN bit
NN
(4)
YYYYYYYYY YN/A
Deep Sleep modes:
Retention
Deep Sleep
Instruction +
DSEN bit +
RETEN
bit
N N Y Y Y N Y N Y Y Y Y N/A Next Instruction
Deep Sleep Instruction +
DSEN bit
N N N Y Y N Y N Y Y Y Y N/A Reset Vector
V
BAT:
with RTCC Hardware N N N Y Y N N N N N N N Y Reset Vector
w/o RTCC Hardware +
by disabling the
RTCC PMD bit
NNNNYNNNNNN N Y
Note 1: If RTCC is otherwise enabled in firmware.
2: Data retention in the DSGPR0, DSGPR1, DSGPR2 and DSGPR3 registers.
3: Deep Sleep WDT in Deep Sleep modes; WDT in all other modes.
4: Some select peripherals may continue to operate in this mode, using either the LPRC or an external clock source.