Datasheet

 2012 Microchip Technology Inc. DS30575A-page 659
PIC18F97J94 FAMILY
FIGURE 31-20: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 31-34: EUSARTx/AUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 31-21: EUSARTx/AUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 31-35: EUSARTx/AUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 T
CKH2DTV SYNC XMIT (MASTER and SLAVE)
Clock High to Data Out Valid — 40 ns
121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns
122 TDTRF Data Out Rise Time and Fall Time — 20 ns
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 T
DTV2CKL SYNC RCV (MASTER and SLAVE)
Data Hold before CKx  (DTx hold time) 10 — ns
126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns
121
121
120
122
TXx/CKx
RXx/DTx
pin
pin
Note: Refer to Figure 31-2 for load conditions.
125
126
TXx/CKx
RXx/DTx
pin
pin
Note: Refer to Figure 31-2 for load conditions.