Datasheet

PIC18F97J94 FAMILY
DS30575A-page 654  2012 Microchip Technology Inc.
FIGURE 31-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 31-29: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SSx
 to SCKx  or SCKx  Input 3 TCY —ns
70A TSSL2WB SSx to Write to SSPBUF 3 TCY —ns
71 TSCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 TDOR SDOx Data Output Rise Time — 25 ns
76 TDOF SDOx Data Output Fall Time — 25 ns
77 T
SSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns
78 T
SCR SCKx Output Rise Time (Master mode) — 25 ns
79 TSCF SCKx Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx Edge — 50 ns
82 T
SSL2DOV SDOx Data Output Valid after SSx  Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SSx
 after SCKx Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKPx = 0)
SCKx
(CKPx = 1)
SDOx
SDIx
70
71 72
82
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
bit 6 - - - - 1 LSb In
80
83
Note: Refer to Figure 31-2 for load conditions.
MSb In