Datasheet

PIC18F97J94 FAMILY
DS30575A-page 652  2012 Microchip Technology Inc.
FIGURE 31-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 31-27: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 20 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 TDOR SDOx Data Output Rise Time — 25 ns
76 TDOF SDOx Data Output Fall Time — 25 ns
78 T
SCR SCKx Output Rise Time (Master mode) — 25 ns
79 TSCF SCKx Output Fall Time (Master mode) — 25 ns
80 T
SCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx Edge — 50 ns
81 T
DOV2SCH,
T
DOV2SCL
SDOx Data Output Setup to SCKx Edge T
CY —ns
SCKx
(CKPx = 0)
SCKx
(CKPx = 1)
SDOx
SDIx
81
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 31-2 for load conditions.
MSb In