Datasheet

 2012 Microchip Technology Inc. DS30575A-page 647
PIC18F97J94 FAMILY
FIGURE 31-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 31-8: BROWN-OUT RESET TIMING
TABLE 31-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — s
31 TWDT Watchdog Timer Time-out Period (no
postscaler)
—4.00— ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 TPWRT Power-up Timer Period — 300 µs — s
34 TIOZ I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
—2—s
35 T
BOR Brown-out Reset Pulse Width 200 — — sVDD  BVDD (see D005)
36 TIRVST Time for Internal Reference
Voltage to become Stable
—25—s
37 T
HLVD High/Low-Voltage Detect Pulse Width 200 — — sVDD  VHLVD
38 TCSD CPU Start-up Time 5 — 10 s
39 TIOBST Time for INTOSC to Stabilize — 1 — s
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 31-2 for load conditions.
VDD
BVDD
35
VBGAP = 1.2V
V
IRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable