Datasheet

PIC18F97J94 FAMILY
DS30575A-page 642  2012 Microchip Technology Inc.
31.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 31-3: EXTERNAL CLOCK TIMING
TABLE 31-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKIN
Frequency
(1)
DC 64 MHz EC Oscillator mode
Oscillator Frequency
(1)
4 16 MHz HS Oscillator mode
4 16 MHz HS + PLL Oscillator mode
1T
OSC External CLKIN Period
(1)
15.6 — ns EC, ECIO Oscillator mode
Oscillator Period
(1)
40 250 ns HS Oscillator mode
62.5 250 ns HS+PLL Oscillator mode
2T
CY Instruction Cycle Time
(1)
62.5 — ns TCY = 4/FOSC
3TOSL,
T
OSH
External Clock in (OSC1)
High or Low Time
10 — ns HS Oscillator mode
4T
OSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 7.5 ns HS Oscillator mode
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4