Datasheet

 2012 Microchip Technology Inc. DS30575A-page 63

PIC18F97J94 FAMILY

3.15.3 CLOCK SYNCHRONIZATION

The Reference Clock Output is enabled only once

(ON = 1). Note that the source of the clock and the

divider values should be chosen prior to the bit being

set to avoid glitches on the REFO output.

Once the ON bit is set, its value is synchronized to the

reference clock domain to enable the output. This

ensures that no glitches will be seen on the output. Sim-

ilarly, when the ON bit is cleared, the output and the

associated output enable signals will be synchronized,

and disabled on the falling edge of the reference clock.

Note that with large divider values, this will cause the

REFO to be enabled for some period after ON is

cleared.

3.15.4 OPERATION IN SLEEP MODE

If any clock source, other than the peripheral clock, is

used as a base reference (i.e., ROSEL<3:0>

 0001),

the user has the option to configure the behavior of the

oscillator in Sleep mode. The RSLP Configuration bit

determines if the oscillator will continue to run in

Sleep. If RSLP = 0, the oscillator will be shut down in

Sleep (assuming no other consumers are requesting

it). If RSLP = 1, the oscillator will continue to run in

Sleep.

The Reference Clock Output is synchronized with the

Sleep signal to avoid any glitches on its output.

3.15.5 MODULE ENABLE SIGNAL

The REFOx module may be enabled or disabled using

the REFOxMD register bit (PMD3, bit 1 or 0). The

module also needs to be turned on using the ON bit

(REFO1CON<7>).

3.15.5.1 Registers and Bits

This module provides the following device registers

and/or bits:

• REFOxCON – Reference Clock Output Control

• REFOxCON1 – Reference Clock Output Control 1

• REFOxCON2 – Reference Clock Output Control 2

• REFOxCON3 – Reference Clock Output Control 3