Datasheet

PIC18F97J94 FAMILY
DS30575A-page 564  2012 Microchip Technology Inc.
REGISTER 28-12: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 U-1 R/WO-1
— — — DSBITEN DSBOREN VBTBOR — RETEN
bit 7 bit 0
Legend: P = Programmable bit WO = Write-Once bit
R = Readable bit W = Writable bit U = Unimplemented bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘1’
bit 4 DSBITEN: DSEN Bit Enable bit
1 = Deep Sleep is controlled by the register bit, DSEN
0 = Deep Sleep operation is always disabled
bit 3 DSBOREN: Deep Sleep BOR Enable bit
1 = DSBOR is enabled in Deep Sleep
0 = DSBOR is disabled in Deep Sleep (does not affect operation in non-Deep Sleep modes)
bit 2 VBTBOR: V
BAT BOR Enable bit
1 = V
BAT BOR is enabled
0 = V
BAT BOR is disabled
bit 1 Unimplemented: Read as ‘1’
bit 0 RETEN: Retention Voltage Regulator Control Enable bit
1 = Retention voltage regulator is disabled
0 = Retention voltage regulator is enabled; regulator power in Sleep mode is controlled by SRETEN
(RCON4<4>)