Datasheet
2012 Microchip Technology Inc. DS30575A-page 561
PIC18F97J94 FAMILY
REGISTER 28-9: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
— — — — MSSPMSK1 MSSPMSK2 LS48MHZ IOL1WAY
bit 7 bit 0
Legend: P = Programmable bit WO = Write-Once bit
R = Readable bit W = Writable bit U = Unimplemented bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
bit 3 MSSPMSK1: MSSP1 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
bit 2 MSSPMSK2: MSSP2 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
bit 1 LS48MHZ: Low-Speed USB Clock Selection bit
1 = 48 MHz system clock is expected; divide-by-8 generates low-speed USB clock
0 = 24 MHz system clock is expected; divide-by-4 generates low-speed USB clock
bit 0 IOL1WAY: IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit can only be set once (provided an unlocking sequence is executed); this prevents
any possible future RP register changes
0 = The IOLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed)