Datasheet

PIC18F97J94 FAMILY

DS30575A-page 560  2012 Microchip Technology Inc.

R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-1 R/WO-1 R/WO-1

WAIT

(1)

BW ABW1 ABW0 EASHFT — CINASEL T5GSEL

bit 7 bit 0

Legend: P = Programmable bit WO = Write-Once bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WAIT: External Bus Wait Enable bit

(1)

1 = Wait selections from WAIT<1:0> (MEMCON<5:4>) are unavailable and the device will not wait

0 = Wait is programmed by WAIT<1:0> (MEMCON<5:4>)

bit 6 BW: Data Bus Width Select bit

1 = 16-Bit External Bus mode

0 = 8-Bit External Bus mode

bit 5-4 ABW<1:0>: External Memory Bus Configuration bits

00 = Extended Microcontroller Mode – 20-Bit Address mode

01 = Extended Microcontroller Mode – 16-Bit Address mode

10 = Extended Microcontroller Mode – 12-Bit Address mode

11 = Microcontroller Mode – External bus is disabled

bit 3 EASHFT: External Address Bus Shift Enable bit

1 = Address shifting is enabled – External address bus is shifted to start at 000000h

0 = Address shifting is disabled – External address bus reflects the PC value

bit 2 Unimplemented: Read as ‘0’

bit 1 CINASEL: CxINA Gate Select bit

1 = C1INA and C3INA are on their default pin locations

0 = C1INA and C3INA are all remapped to pin, RA5

bit 0 T5GSEL: TMR5 Gate Select bit

1 = TMR5 gate is driven by the T5G input

0 = TMR5 gate is driven by the T3G input

Note 1: This bit was previously referred to as ‘WAIT’, but a set condition actually indicates the case where the

EMB does not wait and the name was therefore changed to reflect this. No change in functionality or

polarity occurred, only a change in the name of the register bit.