Datasheet
PIC18F97J94 FAMILY
DS30575A-page 556 2012 Microchip Technology Inc.
REGISTER 28-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
(1,2,3,4)
R/WO-1 U-1 R/WO-0 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1
IESO
—CLKOEN— SOSCSEL FOSC2 FOSC1 FOSC0
bit 7 bit 0
Legend: P = Programmable bit WO = Write-Once bit
R = Readable bit W = Writable bit U = Unimplemented bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IESO: Internal External Switch Over bit
1 = Internal/External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal/External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6 Unimplemented: Read as ‘1’
bit 5 CLKOEN: CLKO Enable Configuration bit
1 = CLKO output signal is active on the OSC2 pin; Primary Oscillator must be disabled or configured
for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11 or 00)
0 = CLKO output disabled
bit 4 Unimplemented: Read as ‘0’
bit 3 SOSCSEL: SOSC Selection Configuration bit
1 = Low-power SOSC circuit is selected (typical I
DD of 1 μA)
0 = Digital (SCLKI) mode
bit 2-0 FOSC<2:0>: Oscillator Selection bits
000 = Fast RC Oscillator (FRC)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010 = Primary Oscillator (MS, HS, EC)
011 = Primary Oscillator with PLL module (MS+PLL, HS+PLL, EC+PLL)
100 = Secondary Oscillator (SOSC)
101 = Low-Power RC Oscillator (LPRC)
110 = Fast RC Oscillator (FRC) divided by 16 (500 kHz)
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
Note 1: The CONFIG2L bits can only be programmed indirectly by programming the Flash Configuration Word.
2: The CONFIG2L is reset to ‘1’ only on V
DD Reset; it is reloaded with the programmed value at any device
Reset.
3: Although CONFIG2L is reset to ‘1’ only on V
DD Reset, these values are not used until after the actual con-
figuration values are read out and stored in the register bits. Therefore, for these bits, the Reset value has
no effect on the operation of the system.
4: Unlike other Configuration registers, the CLKOEN holding register is reset to a ‘0’ on any V
DD Reset. This
prevents the CLKO pin from driving until the actual configuration values are read out and stored in the
register.