Datasheet
2012 Microchip Technology Inc. DS30575A-page 555
PIC18F97J94 FAMILY
REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
R/WO-1 R/WO-1 R/WO-1 U-1 U-1 U-1 U-1 U-1
DEBUG
XINST STVREN — — — — —
bit 7 bit 0
Legend: P = Programmable bit WO = Write-Once bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 DEBUG
: Background Debugger Enable bit
1 = Background debugger is disabled, and RB6 and RB7 are configured as general purpose I/O pins
0 = Background debugger is enabled, and RB6 and RB7 are dedicated to In-Circuit Debug
bit 6 XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode are enabled
0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)
bit 5 STVREN: Stack Overflow Reset Enable bit
1 = Reset on stack overflow/underflow is enabled
0 = Reset on stack overflow/underflow is disabled
bit 4-0 Unimplemented: Read as ‘1’
REGISTER 28-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-1 U-1 U-1 U-1 U-0 R/WO-1 R/WO-1 R/WO-1
— — — — — CP0 BORV BOREN
bit 7 bit 0
Legend: P = Programmable bit WO = Write-Once bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 Unimplemented: Read as ‘—’
bit 3 Unimplemented: Maintain as ‘0’
bit 2 CP0: Code Protection bit 0
1 = Program memory is not code-protected
0 = Program memory is code-protected (and write-protected in test modes)
bit 1 BORV: BOR Trip Point Select bit
1 = BOR trip point is 1.8V
0 = BOR trip point is 2.0V
bit 0 BOREN: Brown-out Reset Enable bit
1 = Brown-out Reset is disabled
0 = Brown-out Reset is enabled outside of Deep Sleep (BORV is always disabled in Deep Sleep)