Datasheet

2012 Microchip Technology Inc. DS30575A-page 549
PIC18F97J94 FAMILY
27.7 Oscillator
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed.
27.8 USB Firmware and Drivers
Microchip provides a number of application-specific
resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.
TABLE 27-4: REGISTERS ASSOCIATED WITH USB MODULE OPERATION
(1)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF
IPR2
OSCFIP SSP2IP BCL2IP USBIP BCL1IP HLVDIP TMR3IP TMR3GIP
PIR2
OSCFIF SSP2IF BCL2IF USBIF BCL1IF HLVDIF TMR3IF TMR3GIF
PIE2
OSCFIE SSP2IE BCL2IE USBIE BCL1IE HLVDIE TMR3IE TMR3GIE
UCON
PPBRST SE0 PKTDIS USBEN RESUME SUSPND
UCFG UTEYE UOEMON
UPUEN UTRDIS FSEN PPB1 PPB0
USTAT
ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI
UADDR
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0
UFRMH
—FRM10FRM9FRM8
UIR
SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF
UIE
SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
UEIR BTSEF
BTOEF DFN8EF CRC16EF CRC5EF PIDEF
UEIE BTSEE
BTOEE DFN8EE CRC16EE CRC5EE PIDEE
UEP0
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP1
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP2
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP3
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP4
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP5
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP6
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP7
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP8
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP9
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP10
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP11
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP12
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP13
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP14
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
UEP15
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
Legend: = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 27-3.