Datasheet

PIC18F97J94 FAMILY
DS30575A-page 528  2012 Microchip Technology Inc.
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong
Buffer Pointers are set to the Even buffers. PPBRST
has to be cleared by firmware. This bit is ignored in
buffering modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table (BDT) will still be available, indicated
within the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the “USB 2.0
Specification”.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry in a Low-Power mode. The input
clock to the SIE is also disabled. This bit should be set
by the software in response to an IDLEIF interrupt. It
should be reset by the microcontroller firmware after an
ACTVIF interrupt is observed. When this bit is active,
the device remains attached to the bus but the
transceiver outputs remain Idle. The voltage on the
V
USB3V3 pin may vary depending on the value of this
bit. Setting this bit before a IDLEIF request will result in
unpredictable bus behavior.
27.2.2 USB CONFIGURATION REGISTER
(UCFG)
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 27-2).The UFCG register
contains most of the bits that control the system-level
behavior of the USB module. These include:
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage
The UCFG register also contains two bits, which aid in
module testing, debugging and USB certifications.
These bits control output enable state monitoring and
eye pattern generation.
27.2.2.1 Internal Transceiver
The USB peripheral has a built-in, “USB 2.0 Specifica-
tion”, full-speed and low-speed capable transceiver,
internally connected to the SIE. This feature is useful
for low-cost, single chip applications. The UTRDIS bit
(UCFG<3>) controls the transceiver; it is enabled by
default (UTRDIS = 0). The FSEN bit (UCFG<2>)
controls the transceiver speed; setting this bit enables
full-speed operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The internal USB transceiver obtains power from the
V
USB3V3 pin. In order to meet USB signalling level
specifications, V
USB3V3 must be supplied with a voltage
source between 3.0V and 3.6V. The best electrical sig-
nal quality is obtained when a 3.3V supply is used and
locally bypassed with a high quality ceramic capacitor
(ex: 0.1 F). The capacitor should be placed as close
as possible to the V
USB3V3 and VSS pins.
V
USB3V3 should always be maintained  VDD. If the
USB module is not used, but RC4 or RC5 are used as
general purpose inputs, VUSB3V3 should still be con-
nected to a power source (such as V
DD). The input
thresholds for the RC4 and RC5 pins are dependent
upon the VUSB3V3 supply level.
The D+ and D- signal lines can be routed directly to
their respective pins on the USB connector or cable (for
hard-wired applications). No additional resistors,
capacitors or magnetic components are required, as
the D+ and D- drivers have controlled slew rate and
output impedance, intended to match with the
characteristic impedance of the USB cable.
In order to achieve optimum USB signal quality, the D+
and D- traces between the microcontroller and USB
connector (or cable) should be less than 19 cm long.
Both traces should be equal in length and they should
be routed parallel to each other. Ideally, these traces
should be designed to have a characteristic impedance
matching that of the USB cable.
Note: While in Suspend mode, a typical bus-
powered USB device is limited to 2.5 mA
of current. This is the complete current
which may be drawn by the PIC MCU
device and its supporting circuitry. Care
should be taken to assure minimum
current draw when the device enters
Suspend mode.
Note: The USB speed, transceiver and pull-up
should only be configured during the
module setup phase. It is not recom-
mended to switch these settings while the
module is enabled.