Datasheet

PIC18F97J94 FAMILY
DS30575A-page 52  2012 Microchip Technology Inc.
loop gain, such that if the circuit functions at these
extremes, the designer can be more assured of proper
operation at other temperatures and supply voltage
combinations. The output sine wave should not be
clipped in the highest gain environment (highest V
DD
and lowest temperature) and the sine output amplitude
should be large enough in the lowest gain environment
(lowest V
DD and highest temperature) to cover the logic
input requirements of the clock, as listed in the device
data sheet. OSC1 may have specified VIL and VIH
levels (refer to the specific product data sheet for more
information).
A method for improving start-up is to use a value of C2
greater than C1. This causes a greater phase shift across
the crystal at power-up, which speeds oscillator start-up.
Besides loading the crystal for proper frequency
response, these capacitors can have the effect of lower-
ing loop gain if their value is increased. C2 can be
selected to affect the overall gain of the circuit. A higher
C2 can lower the gain if the crystal is being overdriven
(also see discussion on Rs). Capacitance values that are
too high can store and dump too much current through
the crystal, so C1 and C2 should not become excessively
large. Unfortunately, measuring the wattage through a
crystal is difficult, but if you do not stray too far from the
suggested values, you should not have to be concerned
with this.
A series resistor, Rs, is added to the circuit if after all
other external components are selected to satisfaction,
and the crystal is still being overdriven. This can be
determined by looking at the OSC2 pin, which is the
driven pin, with an oscilloscope. Connecting the probe
to the OSC1 pin will load the pin too much and nega-
tively affect performance. Remember that a scope
probe adds its own capacitance to the circuit, so this
may have to be accounted for in your design (i.e., if the
circuit worked best with a C2 of 22 pF and the scope
probe was 10 pF, a 33 pF capacitor may actually be
called for). The output signal should not be clipping or
flattened. Overdriving the crystal can also lead to the
circuit jumping to a higher harmonic level, or even,
crystal damage.
The OSC2 signal should be a clean sine wave that
easily spans the input minimum and maximum of the
clock input pin. An easy way to set this is to again test
the circuit at the minimum temperature and maximum
V
DD that the design will be expected to perform in; then,
look at the output. This should be the maximum ampli-
tude of the clock output. If there is clipping, or the sine
wave is distorted near V
DD and VSS, increasing load
capacitors may cause too much current to flow through
the crystal, or push the value too far from the manufac-
turer’s load specification. To adjust the crystal current,
add a trimmer potentiometer between the crystal
inverter output pin and C2, and adjust it until the sine
wave is clean. The crystal will experience the highest
drive currents at the low temperature and high V
DD
extremes.
The trimmer potentiometer should be adjusted at these
limits to prevent overdriving. A series resistor, Rs, of
the closest standard value can now be inserted in place
of the trimmer. If Rs is too high, perhaps more than
20 k, the input will be too isolated from the output,
making the clock more susceptible to noise. If you find
a value this high is needed to prevent overdriving the
crystal, try increasing C2 to compensate or changing
the oscillator operating mode. Try to get a combination
where Rs is around 10 k or less, and load
capacitance is not too far from the manufacturer’s
specification.
3.7 External Clock Input
In EC mode, the OSC1 pin is in a high-impedance state
and can be driven by CMOS drivers. The OSC2 pin can
be configured as either an I/O or the clock output
(F
OSC/4) by selecting the CLKOEN bit (CONFIG2L<5>).
With CLKOEN set (Figure 3-5), the clock output is avail-
able for testing or synchronization purposes. With
CLKOEN clear (Figure 3-6), the OSC2 pin becomes a
general purpose I/O pin. The feedback device between
OSC1 and OSC2 is turned off to save current.
FIGURE 3-5: EXTERNAL CLOCK INPUT
OPERATION (CLKOEN = 1)
FIGURE 3-6: EXTERNAL CLOCK INPUT
OPERATION (CLKOEN = 0)
3.8 Phase Lock Loop (PLL) Branch
The PLL module contains two separate PLL
submodules: PLLM and PLL96MHZ. The PLLM sub-
module is configurable as a 4x, 6x or 8x PLL. The
OSC1
F
OSC/2
Clock from
External System
PIC18F
OSC2 (FOSC/4 output)
OSC1
I/O RA6 (General Purpose I/O)I/O
Clock from
External
PIC18F
System