Datasheet

 2012 Microchip Technology Inc. DS30575A-page 487
PIC18F97J94 FAMILY
FIGURE 22-22: 10-BIT A/D TRANSFER FUNCTION
22.11 Operation During Sleep and Idle
Modes
Sleep and Idle modes are useful for minimizing conver-
sion noise because the digital activity of the CPU,
buses and other peripherals is minimized.
22.11.1 CPU SLEEP MODE WITHOUT RC
A/D CLOCK
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic '0'.
If Sleep occurs in the middle of a conversion, the
conversion is aborted unless the A/D is clocked from its
internal RC clock generator. The converter will not
resume a partially completed conversion on exiting
from Sleep mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
22.11.2 CPU SLEEP MODE WITH RC A/D
CLOCK
The A/D module can operate during Sleep mode if the
A/D clock source is set to the internal A/D RC oscillator
(ADRC = 1). This eliminates digital switching noise
from the conversion. When the conversion is
completed, the DONE bit will be set and the result is
loaded into the A/D Result Buffer n, ADCBUFn.
If the A/D interrupt is enabled (ADIE = 1), the device will
wake-up from Sleep when the A/D interrupt occurs.
Program execution will resume at the A/D Interrupt
Service Routine (ISR). After the ISR completes execu-
tion will continue from the instruction after the Sleep
instruction that placed the device in Sleep mode.
If the A/D interrupt is not enabled, the A/D module will
then be turned off, although the ADON bit will remain
set.
10 0000 0001 (513)
10 0000 0010 (514)
10 0000 0011 (515)
01 1111 1101 (509)
01 1111 1110 (510)
01 1111 1111 (511)
11 1111 1110 (1022)
11 1111 1111 (1023)
00 0000 0000 (0)
00 0000 0001 (1)
Output Code
10 0000 0000 (512)
(VINH – VINL)
V
R-
VR+ – VR-
1024
512 * (VR+ – VR-)
1024
VR+
V
R- +
V
R- +
1023 * (VR+ – VR-)
1024
VR- +
0
(Binary (Decimal))
Voltage Level