Datasheet

 2012 Microchip Technology Inc. DS30575A-page 475
PIC18F97J94 FAMILY
FIGURE 22-15: OUTSIDE WINDOW COMPARISON OPERATION (UNDER THRESHOLD 1)
22.8 Examples
22.8.1 INITIALIZATION
Example 22-1 shows a simple initialization code
example for the A/D module. Operation in Idle mode is
disabled, output data is in unsigned fractional format,
and AV
DD and AVSS are used for VR+ and VR-. The
start of sampling, as well as the start of conversion
(conversion trigger), are performed directly in software.
Scanning of inputs is disabled and an interrupt occurs
after every sample/convert sequence (one conversion
result) with only one channel (AN0) being converted.
The A/D conversion clock is TCY/2.
In this particular configuration, all 16 analog input pins
are set up as analog inputs. It is important to note that
with this A/D module, I/O pins are configured for analog
or digital operation at the I/O port with the ANSn Analog
Select registers. The use of these registers is
described in detail in the I/O Port chapter of the specific
device data sheet.
This example shows one method of controlling a
sample/convert sequence by manually setting and
clearing the SAMP bit (ADCON1L<1>). This method,
among others, is more fully discussed in Section 22.4
“Controlling the Sampling Process” and Section
22.5 “Controlling the Conversion Process”.
ADC1BUF15 —
ADC1BUF14 —
ADC1BUF13 —
ADC1BUF12 —
ADC1BUF11 —
ADC1BUF10 Threshold 2
ADC1BUF9 —
ADC1BUF8 —
ADC1BUF7 —
ADC1BUF6 —
ADC1BUF5 —
ADC1BUF4 —
ADC1BUF3 —
ADC1BUF2 Threshold 1
ADC1BUF1 —
ADC1BUF0 —
Before Conversion and Comparison
AD1CHITL
15 14 13 12 11 10 9 8
00000000
765432 10
000001 00
After Conversion and Comparison
Compare Only
(‘10’)
Compare and
Store (‘01’)
ADC1BUF15 — —
ADC1BUF14 — —
ADC1BUF13 — —
ADC1BUF12 — —
ADC1BUF11 — —
ADC1BUF10 Threshold 2 Threshold 2
ADC1BUF9 — —
ADC1BUF8 — —
ADC1BUF7 — —
ADC1BUF6 — —
ADC1BUF5 — —
ADC1BUF4 — —
ADC1BUF3 — —
ADC1BUF2 Threshold 1 Conversion Value
ADC1BUF1 — —
ADC1BUF0 — —
AD1CHITL
15 14 13 12 11 10 9 8
00000000
76543210
00000000