Datasheet

PIC18F97J94 FAMILY
DS30575A-page 470  2012 Microchip Technology Inc.
The LPENA bit (ADCON5H<6>) allows Threshold
Detect to function with a low-power feature. By design,
Threshold Detect can perform comparison operations
when the device is in Sleep or Idle modes, waking the
CPU when it generates an interrupt. Setting LPENA
configures the device to return to low-power operation
after the interrupt has been serviced.
The Compare Mode bits, CM<1:0> (ADCON5L<1:0>),
select the type of comparison to be performed. Four
types are available:
• The result of the current conversion is greater
than a reference threshold
• The result of the current conversion is less than a
reference threshold
• The result of the current conversion is between
two predefined thresholds (“Inside Window”)
• The result of the current conversion is outside of
the predefined thresholds (“Outside Window”)
The Write Mode bits, WM<1:0> (ADCON5L<3:2>),
determine the disposition of the conversion. Three
options are available:
• Discard the conversion after the comparison has
been performed
• Store the conversion after the comparison has
been performed
• Store the conversion without comparison (Legacy
mode)
22.7.1.1 Buffer Operation And Comparisons
For Buffer Write modes that involve storing conver-
sions (WM<1:0> = 0x), the BUFM and BUFREGEN
bits control how the buffer functions (as a channel
indexed, single FIFO or split FIFO buffer). However,
when the compare and store option is selected
(WM<1:0> = 01), using a FIFO mode may overwrite the
buffers of other channels and cause unpredictable
comparison results. For that reason, always use
Channel Indexed Buffer mode (BUFREGEN = 1) when
using the compare and store option.
22.7.1.2 Buffer Operation In Windowed
Comparisons (Channel Mirroring)
The use of windowed comparisons changes the avail-
able options for the results buffer. To accommodate the
storage of two threshold values, the buffer is automati-
cally split into halves, similar to Split FIFO mode. Buffer
addresses in each half are paired, with the lowest
address in one buffer, matched to the buffer address in
the upper half. (For example, in a 16-word buffer,
ADCBUF0 is paired with ADCBUF9, ADCBUF1 is
paired with ADCBUF10, and so on.) This pairing is
referred to as “channel mirroring”.
Mirroring can obviously be applied only to the lower
A/D channels; for most devices, this corresponds to the
lower half of the external analog channels. This does
not mean that those buffer locations cannot be used for
other purposes. However, storing any other data in a
particular buffer location, where channel mirroring is
being used, may result in misleading comparison
evaluations.
22.7.2 SETTING COMPARISON
THRESHOLDS
The comparison thresholds for Threshold Detect are
set by writing the desired values to an appropriate
location in the A/D results buffer. This can only be done
when the module is deactivated (ADCON1H<7> = 0).
The location of the threshold is determined by the
comparison type. For simple greater than, and less
than, comparisons, the value is written to the buffer
location corresponding to the input channel to be
monitored. For example, if AN0 is to be monitored for a
voltage over a certain level, the ceiling threshold is
stored in ADCBUF0.
The location of the thresholds for windowed compari-
sons are written to two addresses. The lower value is
written to the address corresponding to the monitored
channel. The upper value is stored in the correspond-
ing mirrored address in the upper half of the buffer. To
expand on the previous example, if the conversion on
AN0 is to be a windowed comparison, the floor thresh-
old is stored in ADCBUF0, while the ceiling threshold is
stored in ADCBUF9.
22.7.3 COMPARE HIT REGISTERS
To determine if a particular event has occurred, the A/D
module uses two registers to record match events.
These registers are referred to as the Compare Hit
registers and are designated, ADCHIT1H/L and
ADCHIT0H/L. The registers map their individual bits
sequentially to each of the (up to) 32 analog channels.
If a particular channel in a device is not implemented,
the corresponding Compare Hit bit (CHHn) is not
implemented.
Each bit serves as an event semaphore for its corre-
sponding channel. When the programmed event
occurs on that channel, the bit becomes set and stays
set until it is cleared by the application. It is the user's
responsibility to clear the bits after the application has
evaluated them.
Depending on the event, more than one Compare Hit bit
may be set. The significance of a set bit must be inter-
preted by the application in the context of the Compare
mode selected. Particular examples are covered in
Section 22.7.5 “Comparison Mode Examples”.