Datasheet

 2012 Microchip Technology Inc. DS30575A-page 469
PIC18F97J94 FAMILY
TABLE 22-4: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT INTEGER
FORMATS
TABLE 22-5: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT FRACTIONAL
FORMATS
22.7 Threshold Detect Operation
Threshold Detect is a significant extension of the
Auto-Scan feature offered in previous 10-bit A/D mod-
ules. In addition to being able to repeatedly sample a
predefined sequence of analog channels, Threshold
Detect allows the user to define match conditions
based on the conversion results and generate an inter-
rupt based on these conditions. During normal opera-
tion, this can potentially reduce the amount of CPU
time spent on processing A/D interrupts. For low-power
applications, this can allow the CPU to remain inactive
for longer periods, waking only when specific analog
conditions are met.
When selected by the user, Threshold Detect changes
the operation of the A/D results buffer by making it a
read/write array for both conversion results and com-
parison (threshold) values. It also brings into play the
AD1CHIT registers, which are used to indicate match
conditions. Independently selectable comparison and
buffer storage settings make a wide range of operating
combinations possible.
22.7.1 OPERATING MODES
The operation of Threshold Detect is mostly controlled
by the ADCON5H/L registers. The ASENA bit
(ADCON5L<7>) controls overall operation of
Threshold Detect; setting this bit enables the
functionality.
As with Legacy Auto-Scan operation, the channels to
be included are selected using the ADCSS1H/L,
ADCSS0H/L registers. Setting a particular bit in either
register includes the corresponding channel in an
automatic sequential scan. One or more channels may
be selected. After the channels have been selected,
setting both the CSCNA and ASENA bits to enable a
single scan of the designated channels. The scan itself
is triggered by the trigger source programmed by the
SSRC<3:0> bits.
.
VIN/VREF
10-Bit
Output Code
16-Bit Integer Format/
Equivalent Decimal Value
16-Bit Signed Integer Format/
Equivalent Decimal Value
1023/1024 11 1111 1111 0000 0011 1111 1111 1023 0000 0001 1111 1111 511
1022/1024 11 1111 1110 0000 0011 1111 1110 1022 0000 0001 1111 1110 510

513/1024 10 0000 0001 0000 0010 0000 0001 513 0000 0000 0000 0001 1
512/1024 10 0000 0000 0000 0010 0000 0000 512 0000 0000 0000 0000 0
511/1024 01 1111 1111 0000 0001 1111 1111 511 1111 1111 1111 1111 -1

1/1024 00 0000 0001 0000 0000 0000 0001 1 1111 1110 0000 0001 -511
0/1024 00 0000 0000 0000 0000 0000 0000 0 1111 1110 0000 0000 -512
V
IN/VREF
10-Bit
Output Code
16-Bit Fractional Format/
Equivalent Decimal Value
16-Bit Signed Fractional Format/
Equivalent Decimal Value
1023/1024 11 1111 1111 1111 1111 1100 0000 0.999 0111 1111 1100 0000 0.499
1022/1024 11 1111 1110 1111 1111 1000 0000 0.998 0111 1111 1000 0000 0.498

513/1024 10 0000 0001 1000 0000 0100 0000 0.501 0000 0000 0100 0000 0.001
512/1024 10 0000 0000 1000 0000 0000 0000 0.500 0000 0000 0000 0000 0.000
511/1024 01 1111 1111 0111 1111 1100 0000 0.499 1111 1111 1100 0000 -0.001

1/1024 00 0000 0001 0000 0000 0100 0000 0.001 1000 0000 0100 0000 -0.499
0/1024 00 0000 0000 0000 0000 0000 0000 0.000 1000 0000 0000 0000 -0.500
Note: Legacy Auto-Scan (i.e., sequential
scanning of analog channels on MUX A,
without any comparison) is controlled by
the CSCNA bit (AD1CON2<10>) and
does not depend on the ASEN bit to
function