Datasheet

PIC18F97J94 FAMILY
DS30575A-page 460  2012 Microchip Technology Inc.
The CTMU input is selected by the ADCTMUEN1H/L,
ADCTMUEN0H/L registers. Setting a particular bit in
one of these registers effectively assigns the analog
output from the CTMU to the corresponding A/D input
channel, automatically enabling the CTMU. Many
devices will already have a CH0SAx bit combination
designated for use of the CTMU. This setting discon-
nects the converter from any other load. This channel
should be the one selected by the appropriate
ADCTMUEN bit. If another channel is selected, verify
that any other analog sources are disconnected from
that channel; otherwise, erroneous readings may
result.
For the negative (inverting) input of the amplifier, the
user has up to eight options, selected by the
CH0NA<2:0> and CH0NB<2:0> bits (ADCHS0L<7:5>
and ADCHS0H<7:5>, respectively). Options typically
include the device ground (AV
SS), the current VR-
source designated by the NVCFG0 bit
(ADCON2H<5>), and one or more of the external
analog input channels. As with the non-inverting inputs,
the options vary by device family.
22.3.5.2 Alternating MUX A And MUX B Input
Selections
By default, the A/D Converter only samples and con-
verts the inputs selected by MUX A. The ALTS bit
(ADCON2L<0>) enables the module to alternate
between two sets of inputs selected by MUX A and
MUX B during successive samples.
If the ALTS bit is '0', only the inputs specified by the
CH0SAx and CH0NAx bits are selected for sampling.
When the ALTS bit is '1', the module will alternate
between the MUX A inputs on one sample and the
MUX B inputs on the subsequent sample.
If the ALTS bit is '1' on the first sample/convert
sequence, the inputs specified by the CH0SAx and
CH0NAx bits are selected for sampling. On the next
sample/convert sequence, the inputs specified by the
CH0SBx and CH0NBx bits are selected for sampling.
This pattern repeats for subsequent sample conversion
sequences.
22.3.5.3 Scanning Through Several Inputs
When using MUX A to select analog inputs, the A/D
module has the ability to scan multiple analog chan-
nels. When the CSCNA bit (ADCON2H<>) is set, the
CH0SA bits are ignored and the channels specified by
the ADCSS1H/L, ADCSS0H/L registers are sequen-
tially sampled.
Each bit in the ADCSS1H/L registers and ADCSS0H/L
registers (when implemented) corresponds to one of
the analog channels. If a bit in the ADCSS0H/L or
ADCSS1H/L registers is set, the corresponding analog
channel is included in the scan sequence. Inputs are
always scanned from lower to higher numbered inputs,
starting at the first selected channel after each interrupt
occurs.
The ADCSS1H/L, ADCSS0H/L registers' bits specify
the positive input of the channel. The CH0NAx bits still
select the negative input of the channel during
scanning.
Scanning is only available on the MUX A input
selection. The MUX B input selection, as specified by
the CH0SBx bits, will still select the alternating input.
When alternated sampling between MUX A and MUX
B is selected (ALTS = 1), the input will alternate
between a set of scanning inputs specified by the
ADCSS1H/L, ADCSS0H/L registers, and a fixed input
specified by the CH0SBx bits.
Automatic scanning can be used in conjunction with the
Threshold Detect feature to determine if one or more
analog channels meet a predetermined set of condi-
tions while the CPU is inactive. This is described in
detail in Section 22.7 “Threshold Detect Operation”.
22.3.5.4 Internal Channels In Low-power
Modes
While the A/D module can scan and convert analog
inputs in low-power modes, some internal analog
inputs may be unavailable in Sleep mode. The main
examples are the CTMU module, the internal band gap
voltage source and the on-chip voltage regulator (for
those devices that include one). The A/D module
provides a method to make these resources available
automatically through the CTMUREQ bit
(ADCON5H<5>). Setting one or more of these bits
causes the corresponding internal analog source(s) to
become active during a channel scan.
22.3.6 ENABLING THE MODULE
When the ADON bit (ADCON1H<7>) is set, the module
is fully powered and functional. When ADON is '0', the
module is disabled. Although the digital and analog
portions of the circuit are turned off for maximum
current savings, the contents of all registers are
maintained.
Note 1: If the number of scanned inputs selected
is greater than the number of samples
taken per interrupt, the higher numbered
inputs will not be sampled.
2: If the CTMU channel is to be included in
a scan operation, verify that the proper
analog input channel is selected and that
the AD1CTMEN register(s) are correctly
configured. For more information, see
Section 22.3.5.1 “Configuring MUX A
And MUX B Inputs”.