Datasheet

PIC18F97J94 FAMILY

DS30575A-page 46  2012 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 HC/R/W-0 HS/HC/R-0

ON —SIDL OERSLP

(1)

— DIVSW_EN ACTIVE

bit 7 bit 0

Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ON: Reference Clock Output Enable bit

1 = Reference clock module is enabled

0 = Reference clock module is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5 SIDL: Peripheral Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 4 OE: Reference Clock Output Enable bit

1 = Reference clock is driven out on REFOx pin

0 = Reference clock is NOT driven out on REFOx pin

bit 3 RSLP: Reference Clock Output Run in Sleep bit

(1)

1 = Reference Clock Output continues to run in Sleep

0 = Reference Clock Output is disabled in Sleep

bit 2 Unimplemented: Read as ‘0’

bit 1 DIVSW_EN: Clock RODIV Switch Enabled status bit

1 = Clock Divider Switching currently in progress

0 = Clock Divider Switching has completed

bit 0 ACTIVE: Reference Clock Output Request Status bit

1 = Reference clock request is active (user should not update the ROSEL and RODIV register fields)

0 = Reference clock request is not active (user may update the ROSEL and RODIV register fields)

Note 1: This bit has no effect when ROSEL<3:0> = 0000/0001, as the system clock and peripheral clock are

always disabled in Sleep mode on PIC18 devices.