Datasheet

 2012 Microchip Technology Inc. DS30575A-page 459
PIC18F97J94 FAMILY
22.3.3 SELECTING THE A/D CONVERSION
CLOCK
The A/D Converter has a maximum rate at which
conversions may be completed. An analog module
clock, TAD, controls the conversion timing. The A/D
conversion requires 14 clock periods (14 TAD) for a
12-bit conversion and 12 clock periods (12 TAD) for a
10-bit conversion. The A/D clock is derived from the
device instruction clock.
The period of the A/D conversion clock is software
selected using a 6-bit counter. There are 64 possible
options for TAD, specified by the ADCSX bits in the
ADCON3L register. Equation 22-1 gives the TAD value
as a function of the ADCSx control bits and the device
instruction cycle clock period, TCY. For correct A/D
conversions, the A/D conversion clock (TAD) must be
selected to ensure a minimum TAD time, as specified
by the device family data sheet.
EQUATION 22-1: A/D CONVERSION CLOCK
PERIOD
The A/D Converter also has its own dedicated RC clock
source that can be used to perform conversions. The
A/D RC clock source should be used when conversions
are performed while the device is in Sleep mode. The
RC oscillator is selected by setting the ADRC bit
(ADCON3H<7>). When the ADRC bit is set, the
ADCSx bits have no effect on A/D operation.
22.3.4 CONFIGURING ANALOG PORT
PINS
The A/D module does not have an internal provision to
configure port pins for analog operation. Instead, input
pins are configured as analog inputs through the
Analog Select registers (ANSn, where ‘n’ is the port
name). A pin is configured as an analog input when the
corresponding ANSn bit is set. By default, pins with
multiplexed analog and digital functions are configured
as analog pins on device Reset.
For external analog inputs, both the ANSn register and
the corresponding TRIS register bits control the opera-
tion of the A/D port pins. The port pins that will function
as analog inputs must also have their corresponding
TRIS bits set, specifying the pins as inputs. After a
device Reset, all TRIS bits are set. If the I/O pin asso-
ciated with an A/D channel is configured as a digital
output (TRIS bit is cleared), while the pin is configured
for Analog mode, the port digital output level (VOH or
VOL) will be converted.
22.3.5 INPUT CHANNEL SELECTION
The A/D Converter incorporates two independent sets
of input multiplexers (MUX A and MUX B) that allow
users to choose which analog channels are to be sam-
pled. The inputs specified by the CH0SAx and CH0NAx
bits are collectively called the MUX A inputs. The inputs
specified by the CH0SBx and CH0NBx bits are collec-
tively called the MUX B inputs.
Functionally, MUX A and MUX B are very similar to each
other. Both multiplexers allow any of the analog input
channels to be selected for individual sampling and
allow selection of a negative reference source for differ-
ential signals. In addition, MUX A can be configured for
sequential analog channel scanning. This is discussed
in more detail in Section 22.3.5.1 “Configuring MUX A
And MUX B Inputs” and Section 22.3.5.3 “Scanning
Through Several Inputs”.
22.3.5.1 Configuring MUX A And MUX B
Inputs
The user may select any one of up to 32 inputs avail-
able to the A/D Converter as the positive input of the
S/H amplifier. For MUX A, the CH0SA<4:0> bits
(ADCHS0L<4:0>) normally select the analog channel
for the positive input. For MUX B, the positive channel
is selected by the CH0SB<4:0> bits (ADCHS0H<4:0>).
All of the external analog channels are available as
positive inputs. In addition to the external inputs, these
may also include device supply voltage (AV
DD), the
logic core supply voltage (V
DDCORE), the internal band
gap voltage (VBG) and/or multiples or fractions of VBG.
One or more additional input channels are used for the
CTMU. These selections leave the A/D disconnected
from all other inputs. The options vary by device family;
refer to the specific device data sheet for details.
TCY (ADCSx + 1)
ADCS
X =– 1
T
AD
TCY
Note: Based on TCY = 2/FOSC; Doze mode
TAD =
and PLL are disabled.
Note 1: When reading a PORT register, any pin
configured as an analog input reads as
‘0’.
2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume current that is out of
the device’s specification.
Note: Different PIC18F devices will have
different numbers of analog inputs. Verify
the analog input availability against the
particular device’s data sheet.