Datasheet

 2012 Microchip Technology Inc. DS30575A-page 457
PIC18F97J94 FAMILY
22.2.1 OPERATION AS A STATE MACHINE
The A/D conversion process can be thought of in terms
of a finite state machine (Figure 22-3). The sample
state represents the time that the input channel is
connected to the S/H amplifier and the signal is passed
to the converter input. The convert state is transitory.
The module enters this state as soon as it exits the
sample state and transitions to a different state when
that is done. The inactive state is the default state prior
to module initialization and following a software-con-
trolled conversion; it can be avoided in operation by
using Auto-Sample mode. Machine states are identi-
fied by the state of several control and status bits in
ADCON1H/L.
If the module is configured for Auto-Sample mode, the
operation “ping-pongs” continuously between the
sample and convert states. The module automatically
selects the input channels to be sampled (if channel
scanning is enabled), while the selected conversion
trigger source paces the entire operation. Any time that
Auto-Sample mode is not used for conversion, it is
available for the sample state. The user needs to make
certain that acquisition time is sufficient, in addition to
accounting for the normal concerns about system
throughput.
Whenever the issue of sampling time is important, the
significant event is the transition from sample to con-
vert state. This is the point where the Sample-and-Hold
aperture closes, and it is essentially the signal value at
this instant, which is applied to the A/D for conversion
to digital.
FIGURE 22-3: A/D MODULE STATE MACHINE MODEL
INACTIVE
SAMPLE
CONVERT
SAMP = 0
DONE = 1
SAMP = 0
DONE =
0
SAMP = 1
DONE = x
SAMP 0
→1
ASAM = 1
and DONE 0→1
ASAM = 0
and
SSRCx Trigger Events
DONE 0
→1
Device Reset
Legend: HW = Automatic Hardware event; SW = Software Controlled event.
Note: See Register 22-5 for definitions of the ASAM, SAMP, DONE and SSRC<3:0> bits.
SW
HW
HW
ASAM 0
→1 or