Datasheet

 2012 Microchip Technology Inc. DS30575A-page 455
PIC18F97J94 FAMILY
REGISTER 22-24: ADCTMUEN0H: CTMU ENABLE REGISTER 0 HIGH (HIGH WORD)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN15 CTMUEN14 CTMUEN13 CTMUEN12 CTMUEN11 CTMUEN10 CTMUEN9 CTMUEN8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CTMUEN<15:8>: CTMU Enabled During Conversion bits
1 = CTMU is enabled and connected to the selected channel during conversion
0 = CTMU is not connected to this channel
Note 1: The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.
REGISTER 22-25: ADCTMUEN0L: CTMU ENABLE REGISTER 0 LOW (LOW WORD)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN7 CTMUEN6 CTMUEN5 CTMUEN4 CTMUEN3 CTMUEN2 CTMUEN1 CTMUEN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 CTMUEN<7:0>: CTMU Enabled During Conversion bits
1 = CTMU is enabled and connected to the selected channel during conversion
0 = CTMU is not connected to this channel
Note 1: The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.