Datasheet

PIC18F97J94 FAMILY
DS30575A-page 454  2012 Microchip Technology Inc.
REGISTER 22-22: ADCTMUEN1H: CTMU ENABLE REGISTER 1 HIGH (HIGH WORD)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CTMUEN30 CTMUEN29 CTMUEN28 CTMUEN27 CTMUEN26 CTMUEN25 CTMUEN24
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-0 CTMUEN<30:24>: CTMU Enabled During Conversion bits
1 = CTMU is enabled and connected to the selected channel during conversion
0 = CTMU is not connected to this channel
Note 1: The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.
REGISTER 22-23: ADCTMUEN1L: CTMU ENABLE REGISTER 1 LOW (LOW WORD)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN23 CTMUEN22 CTMUEN21 CTMUEN20 CTMUEN19 CTMUEN18 CTMUEN17 CTMUEN16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 CTMUEN<23:16>: CTMU Enabled During Conversion bits
1 = CTMU is enabled and connected to the selected channel during conversion
0 = CTMU is not connected to this channel
Note 1: The actual number of channels available depends on which channels are implemented on a specific
device; refer to the device data sheet for details. Unimplemented channels are read as ‘0’.