Datasheet

 2012 Microchip Technology Inc. DS30575A-page 45
PIC18F97J94 FAMILY
3.4 Reference Clock Output Control
Module
The PIC18F97J94 family has two Reference Clock
Output (REFO) modules. Each of the Reference Clock
Output modules provides the user with the ability to
send out a programmed output clock onto the
REFO1or REFO2 pins.
3.4.1 REFERENCE CLOCK SOURCE
The module provides the ability to select one of the
following clock sources:
• Primary Crystal Oscillator (POSC)
• Secondary Crystal Oscillator (SOSC)
• 32.768 kHz Internal Oscillator (INTOSC)
• Fast Internal Oscillator (FRC)
It includes a programmable clock divider with ratios
ranging from 1:1 to 1:65534.
When the clock source is a crystal or internal oscillator,
the RSLP bit can be set to continue REFO operation
while the device is in Sleep Mode.
3.4.2 CLOCK SYNCHRONIZATION
The Reference Clock Output is enabled only once
(ON = 1). Note that the source of the clock and the
divider values should be chosen prior to the bit being
set to avoid glitches on the REFO output.
Once the ON bit is set, its value is synchronized to the
Reference Clock Output domain to enable the output.
This ensures that no glitches will be seen on the output.
Similarly, when the ON bit is cleared, the output and the
associated output enable signals will be synchronized
and disabled on the falling edge of the Reference Clock
Output. Note that with large divider values, this will
cause the REFO to be enabled for some period after
ON is cleared.
3.4.3 OPERATION IN SLEEP MODE
If any clock source, other than the peripheral clock, is
used as a base reference (i.e., ROSEL<3:0>  0001),
the user has the option to configure the behavior of the
oscillator in Sleep mode. The RSLP Configuration bit
determines if the oscillator will continue to run in Sleep.
If RSLP = 0, the oscillator will be shut down in Sleep
(assuming no other consumers are requesting it). If
RSLP = 1, the oscillator will continue to run in Sleep.
The Reference Clock Output is synchronized with the
Sleep signal to avoid any glitches on its output.
3.4.3.1 Module Enable Signal
The REFOx module may be enabled or disabled using
the REFOxMD register bit, which holds the REFOx
module in Reset, or the ON register bit, which does not.
3.4.3.2 Registers and Bits
This module provides the following device registers
and/or bits:
• REFOxCON – Reference Clock Output Control
Register
• REFOxCON1 – Reference Clock Output Control 1
Register
• REFOxCON2 – Reference Clock Output Control 2
Register
• REFOxCON3 – Reference Clock Output Control 3
Register
In addition, the REFOxCON1 module needs to be
enabled by clearing the REFOxMD disable bit
(PMD3<1>).
3.4.3.3 Interrupts
This module does not generate any interrupts.
Note: Throughout this section, references to
register and bit names that may be associ-
ated with specific Reference Clock Output
modules are referred to generically by the
use of ‘x’ in place of the specific module
number. Thus, “REFOxCON” might refer to
the control register for either REFO1 or
REFO2.