Datasheet

 2012 Microchip Technology Inc. DS30575A-page 443

PIC18F97J94 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits

1x = Unimplemented, do not use

01 =External V

REF+

00 =AV

bit 5 NVCFG0: Converter Negative Voltage Reference Configuration bit

1 =External VREF-

0 =AV

bit 4 OFFCAL: Offset Calibration Mode Select bit

1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS

0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs

bit 3 BUFREGEN: A/D Buffer Register Enable bit

1 = Conversion result is loaded into the buffer location determined by the converted channel

0 = A/D result buffer is treated as a FIFO

bit 2 CSCNA: Scan Input Selections for CH0+ During Sample A bit

1 =Scans inputs

0 = Does not scan inputs

bit 1-0 Unimplemented: Read as ‘0’