Datasheet

 2012 Microchip Technology Inc. DS30575A-page 437
PIC18F97J94 FAMILY
22.1 Registers
The 12-bit A/D converter module uses up to 75
registers for its operation. All registers are mapped in
the data memory space.
22.1.1 CONTROL REGISTERS
Depending on the specific device, the module has up to
twelve control and status registers:
• ADCON1H/L: A/D Control Registers
• ADCON2H/L: A/D Control Registers
• ADCON3H/L: A/D Control Registers
• ADCON5H/L: A/D Control Registers
• ADCHS0H/L: A/D Input Channel Select Registers
• ADCHITH1H/L and ADCHITH0H/L: A/D Scan
Compare Hit Registers
• ADCSS1H/L and ADCSS0H/L: A/D Input Scan
Select Registers
• ADCTMUEN1H/L and ADCTMUEN0H/L: CTMU
Enable Register
The ADCON1H/L, ADCON2H/L and ADCON3H/L reg-
isters control the overall operation of the A/D module.
This includes enabling the module, configuring the con-
version clock and voltage reference sources, selecting
the sampling and conversion triggers, and manually
controlling the sample/convert sequences. The
ADCON5H/L registers specifically controls features of
Threshold Detect operation, including its functioning in
power-saving modes.
The ADCHS0H/L registers selects the input channels
to be connected to the S/H amplifier. It also allows the
choice of input multiplexers and the selection of a
reference source for differential sampling.
The ADCHITH1H/L and ADCHITH0H/L registers are
semaphore registers used with Threshold Detect
operations. The status of individual bits, or bit pairs in
some cases, indicate if a match condition has occurred.
Their use is described in more detail in Section 22.7
“Threshold Detect Operation”. ADCHITH0H/L is
always implemented, whereas ADCHITH1H/L may not
be implemented in devices with 16 channels or less.
The ADCSS0H/L/L registers select the channels to be
included for sequential scanning. The
ADCTMUEN1H/L/L registers select the channel(s) to
be used by the CTMU during conversions. Selecting a
particular channel allows the A/D Converter to control
the CTMU (particularly, its current source) and read its
data through that channel. ADCTMUEN0H/L is always
implemented, whereas ADCTMUEN1H/L may not be
implemented in devices with 16 channels or less.
22.1.2 A/D RESULT BUFFERS
The module incorporates a multi-word, dual port RAM,
called ADCBUF. The buffer is composed of at least the
same number of word locations as there are external
analog channels for a particular device, with a
maximum number of 26. The number of buffer
addresses is always even. Each of the locations is
mapped into the data memory space and is separately
addressable.The buffer locations are referred to as
ADCBUF0H/L through ADCBUFnH/L (up to 26).
The A/D result buffers are both readable and writable.
When the module is active (ADCON1H<7> = 1), the
buffers are read-only, and store the results of A/D
conversions. When the module is inactive
(ADCON1H<7> = 0), the buffers are both readable and
writable. In this state, writing to a buffer location
programs a conversion threshold for Threshold Detect
operations, as described in Section 22.7.2 “Setting
Comparison Thresholds”.