Datasheet

 2012 Microchip Technology Inc. DS30575A-page 431
PIC18F97J94 FAMILY
21.5 Infrared Support
This module provides support for two types of infrared
USART port implementations:
• IrDA clock output to support an external IrDA
encoder/decoder device
• Full implementation of the IrDa encoder and
decoder as part of the USART logic
Since the 16x clock is required to perform the IrDA
encoding, both by this module and the external trans-
mitter, this feature only works in the 16x Baud Rate
mode and is not available in the 4x mode.
21.5.1 EXTERNAL IrDA SUPPORT – IRDA
CLOCK OUTPUT
The 16x Baud Clock is provided on the BCLK (Baud
Clock) pin if the EUSARTx is enabled (SPEN = 1); it is
configured for Asynchronous mode (SYNC = 0) when
Clock Source Select is active (CSRC = 1). Note that
the BCLK can be active in regular or IrDA mode (IREN
bit is ignored).
21.5.1.1 BCLK Output
The timing of the Baud Clock (BCLK) output is inde-
pendent of the 16x or 4x Baud Rate mode, resulting in
the same output for a particular BRG value (since the
4x mode is four times faster, but has four times less
pulses per period).
When the BCLK pin mode is active, the RXx Baud
Rate Generator will be turned on, independent of a
TXx or RXx operation. This will cause the RXx stream
to synchronize to the already running RXx Baud Clock.
This is acceptable only when BCLK is enabled for use.
The BCLK output goes inactive and stays low during
Sleep mode.
The BCLK pin is taken over by the EUSARTx module
and forced as an output, irrespective of port latch and
TRIS latch bits. BCLK remains an output as long as
USART is kept enabled in this mode.
FIGURE 21-14: BCLK OUTPUT vs. BRG PROGRAMMING
(BRG + 1)
[INT(BRG + 1)/2]
16x or 4x Clock
BCLK @ BRG = 0
BCLK @ BRG = 1
BCLK @ BRG = 2
BCLK @ BRG = 3
BCLK @ BRG = 4
BCLK @ BRG = 5
BCLK @ BRG = n
Note: The BCLK has 50% duty cycle only for odd BRG values. This is due to having all BCLK edges synchronous to the
rising edge of the 16x/4x clock.