Datasheet

PIC18F97J94 FAMILY
DS30575A-page 416  2012 Microchip Technology Inc.
21.1 Baud Rate Generator (BRG)
The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSARTx. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the period
of a free-running timer. In Asynchronous mode, bits,
BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>),
also control the baud rate. In Synchronous mode, BRGH
is ignored. Table 21-1 shows the formula for computation
of the baud rate for different EUSARTx modes which only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
OSC, the nearest
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Tab le 21 -1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 21-1. Typical baud rates
and error values for the various Asynchronous modes
are shown in Tabl e 21 -2 . It may be advantageous to use
the high baud rate (BRGH = 1) or the 16-bit BRG to
reduce the baud rate error, or achieve a slow baud rate
for a fast oscillator frequency.
Writing a new value to the SPBRGHx:SPBRGx
registers causes the BRG timer to be reset (or cleared).
This ensures the BRG does not wait for a timer over-
flow before outputting the new baud rate. When
operated in the Synchronous mode, SPBRGH:SPBRG
values of 0000h and 0001h are not supported. In the
Asynchronous mode, all BRG values may be used.
21.1.1 OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRGx register pair.
21.1.2 SAMPLING
The data on the RXx pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RXx pin.
TABLE 21-1: BAUD RATE FORMULAS
EXAMPLE 21-1: CALCULATING BAUD RATE ERROR
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous F
OSC/[64 (n + 1)]
001 8-bit/Asynchronous
F
OSC/[16 (n + 1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
F
OSC/[4 (n + 1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG:
Desired Baud Rate = F
OSC/(64 ([SPBRGHx:SPBRGx] + 1))
Solving for SPBRGHx:SPBRGx:
X = ((F
OSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%