Datasheet

PIC18F97J94 FAMILY
DS30575A-page 40  2012 Microchip Technology Inc.
3.2.1 CLOCK SWITCHING MODE
CONFIGURATION BITS
The FSCMx Configuration bits (CONFIG3L<5:4>) are
used to jointly configure device clock switching and the
Fail-Safe Clock Monitor (FSCM). Clock switching is
enabled only when FSCM1 is programmed (‘0’). The
FSCM is enabled only when FSCM<1:0> are both
programmed (‘00’).
3.2.2 OSC1 AND OSC2 PIN FUNCTIONS
IN NON-CRYSTAL MODES
When the Primary Oscillator on OSC1 and OSC2 is not
configured as the clock source (POSCMD<1:0> = 11),
the OSC1 pin is automatically reconfigured as a
digital I/O. In this configuration, as well as when the
Primary Oscillator is configured for EC mode
(POSCMD<1:0> = 00), the OSC2 pin can also be
configured as a digital I/O by programming the
CLKOEN Configuration bit (CONFIG2L<5>).
When CLKOEN is unprogrammed (‘1’), a F
OSC/4 clock
output is available on OSC2 for testing or synchroniza-
tion purposes. With CLKOEN programmed (‘0’), the
OSC2 pin becomes a general purpose I/O pin. In both
of these configurations, the feedback device between
OSC1 and OSC2 is turned off to save current.
3.3 Control Registers
The operation of the oscillator is controlled by six
Special Function Registers (SFRs):
• OSCCON
• OSCCON2
• OSCCON3
• OSCCON4
• ACTCON
• OSCTUNE
3.3.1 OSCILLATOR CONTROL REGISTER
(OSCCON)
The OSCCON register (Register 3-1) is the main con-
trol register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
The COSCx (OSCCON<6:4>) status bits are read-only
bits that indicate the current oscillator source the
device is operating from. The COSCx bits default to the
Internal Fast RC Oscillator with Postscaler (FRCDIV),
configured for 4 MHz, on a Power-on Reset (POR) and
Master Clear Reset (MCLR
). A clock switch will
automatically be performed to the new oscillator source
selected by the FOSCx Configuration bits
(CONFIG2L<2:0>). The COSCx bits will change to indi-
cate the new oscillator source at the end of a clock
switch operation.
The NOSCx status bits select the clock source for the
next clock switch operation. On POR and MCLR
s,
these bits automatically select the oscillator source
defined by the FOSCx Configuration bits. These bits
can be modified by software.
Setting the CLKLOCK bit (OSCCON2<7>) prevents
clock switching if the FSCM1 Configuration bit is set. If
the FSCM1 bit is clear, the CLKLOCK bit state is
ignored and clock switching can occur.
The IOLOCK bit (OSCCON2<6>) is used to unlock the
Peripheral Pin Select (PPS) feature; it has no function
in the system clock’s operation.
The LOCK status bit (OSCCON2<5>) is read-only and
indicates the status of the PLL circuit. It is set when the
PLL achieves a frequency lock and is reset when a
valid clock switching sequence is initiated. It reads as
‘0’ whenever the PLL is not used as part of the current
clock source.
The CF status bit (OSCCON2<3>) is a readable/clearable
status bit that indicates a clock failure; it is reset whenever
a valid clock switch occurs.
The POSCEN bit (OSCCON2<2>) is used to control
the operation of the Primary Oscillator in Sleep mode.
Setting this bit bypasses the normal automatic
shutdown of the oscillator whenever Sleep mode is
invoked.
The Secondary Oscillator can be turned on by a variety
of options:
• SOSCGO – OSCCON2<1>
• SOSCSEL – CONFIG2L<3>
• FOSC<2:0> – CONFIG2L<2:0>
• DSWDTOSC – CONFIG8H<1>
• RTCEN – RTCCON1<7>
• SOSCEN – T1CON<3>, T3CON<3> or
T5CON<3>
The ACTCON register (Register 3-10) controls the
Active Clock Tuning features.