Datasheet

 2012 Microchip Technology Inc. DS30575A-page 393
PIC18F97J94 FAMILY
FIGURE 20-16: I
2
C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDAx SCLx SSPxIF (PIR1<3> or PIR3<7>) BF (SSPxSTAT<0>)
S
123456789 123456789 12345 789
P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1 A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware when SSPxADD is updated with low byte of address after falling edge
UA (SSPxSTAT<1>)
Clock is held low until update of SSPxADD has taken place
UA is set indicating that the SSPxADD needs to be updated
UA is set indicating that SSPxADD needs to be updated
Cleared by hardware when SSPxADD is updated with high byte of address after falling edge
SSPxBUF is written with contents of SSPxSR
Dummy read of SSPxBUF to clear BF flag
ACK
CKP (SSPxCON<4>)
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master terminates transfer
D2
6
ACK
Cleared in software
Cleared in software
SSPOV (SSPxCON1<6>)
CKP written to ‘1’
Note: An update of the
SSPxADD register before
Note: An update of
the SSPxADD register
in software
Clock is held low until update of SSPxADD has taken place
of ninth clock
of ninth clock
SSPOV is set because SSPxBUF is still full. ACK is not sent.
Dummy read of SSPxBUF to clear BF flag
Clock is held low until CKP is set to ‘1’
Clock is not held low because ACK = 1