Datasheet

 2012 Microchip Technology Inc. DS30575A-page 381
PIC18F97J94 FAMILY
20.5.4.1 Address Masking Modes
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an inter-
rupt. It is possible to mask more than one address bit at
a time, which greatly expands the number of addresses
Acknowledged.
The I
2
C slave behaves the same way, whether address
masking is used or not. However, when address mask-
ing is used, the I
2
C slave can Acknowledge multiple
addresses and cause interrupts. When this occurs, it is
necessary to determine which address caused the
interrupt by checking the SSPxBUF.
The PIC18F97J94 family of devices is capable of using
two different Address Masking modes in I
2
C slave
operation: 5-Bit Address Masking and 7-Bit Address
Masking. The Masking mode is selected at device con-
figuration using the MSSPMSK<2:1> Configuration
bits. The default device configuration is 7-Bit Address
Masking.
Both Masking modes, in turn, support address masking
of 7-bit and 10-bit addresses. The combination of
Masking modes and addresses provides different
ranges of Acknowledgable addresses for each
combination.
While both Masking modes function in roughly the
same manner, the way they use address masks are
different.
20.5.4.2 5-Bit Address Masking Mode
As the name implies, 5-Bit Address Masking mode
uses an address mask of up to 5 bits to create a range
of addresses to be Acknowledged, using bits, 5 through
1, of the incoming address. This allows the module to
Acknowledge up to 31 addresses when using 7-bit
addressing, or 63 addresses with 10-bit addressing
(see Example 20-3). This Masking mode is selected
when the MSSPMSK<2:1> Configuration bits are
programmed (‘00’).
The address mask in this mode is stored in the
SSPxCON2 register, which stops functioning as a con-
trol register in I
2
C Slave mode (Register 20-10). In 7-Bit
Address Masking mode, Address Mask bits, MSK<5:1>
(SSPxMSK<5:1>), mask the corresponding address
bits in the SSPxADD register. For any MSK bits that are
set (MSK<n> = 1), the corresponding address bit is
ignored (SSPxADD<n> = x). For the module to issue
an address Acknowledge, it is sufficient to match only
on addresses that do not have an active address mask.
In 10-Bit Address Masking mode, the MSK<5:2> bits
mask the corresponding address bits in the SSPxADD
register. In addition, MSK1 simultaneously masks the
two LSbs of the address (SSPxADD<1:0>). For any
MSKx bits that are active (MSK<n> = 1), the corre-
sponding address bit is ignored (SPxADD<n> = x).
Also note that although in 10-Bit Address Masking
mode, the upper address bits re-use part of the
SSPxADD register bits. The address mask bits do not
interact with those bits; they only affect the lower
address bits.
EXAMPLE 20-3: ADDRESS MASKING EXAMPLES IN 5-BIT MASKING MODE
Note 1: MSK1 masks the two Least Significant bits
of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
7-Bit Addressing:
SSPxADD<7:1> = A0h (1010000) (SSPxADD<0> is assumed to be ‘0’)
MSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPxADD<7:0> = A0h (10100000) (The two MSb of the address are ignored in this example, since
they are not affected by masking.)
MSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh