Datasheet

 2012 Microchip Technology Inc. DS30575A-page 379

PIC18F97J94 FAMILY

C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING

MODE)

(1)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0

(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 MSK<7:0>: Slave Address Mask Select bits

1 = Masking of corresponding bit of SSPxADD is enabled

0 = Masking of corresponding bit of SSPxADD is disabled

Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSPx

operating modes. See Section 20.5.4.3 “7-Bit Address Masking Mode” for more details.

2: MSK0 is not used as a mask bit in 7-bit addressing.