Datasheet

 2012 Microchip Technology Inc. DS30575A-page 377
PIC18F97J94 FAMILY
REGISTER 20-10: SSPxCON2: MSSPx CONTROL REGISTER 2 (I
2
C™ SLAVE MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT
(1)
ACKEN
(1)
RCEN
(1)
PEN
(1)
RSEN
(1)
SEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address is disabled
bit 6 ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(1)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
automatically cleared by hardware
0 = Acknowledge sequence is Idle
bit 3 RCEN: Receive Enable bit (Master Receive mode only)
(1)
1 = Enables Receive mode for I
2
C
0 = Receive is Idle
bit 2 PEN: Stop Condition Enable bit
(1)
1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Stop condition is Idle
bit 1 RSEN: Repeated Start Condition Enable bit
(1)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
0 = Repeated Start condition is Idle
bit 0 SEN: Stretch Enable bit
(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: If the I
2
C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).