Datasheet

PIC18F97J94 FAMILY

DS30575A-page 376  2012 Microchip Technology Inc.

C MASTER MODE)

R/HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ACKTIM: Acknowledge Time Status bit

Unused in Master mode.

bit 6 PCIE: Stop Condition Interrupt Enable bit

(1)

1 = Enable interrupt on detection of Stop condition

0 = Stop detection interrupts are disabled

bit 5 SCIE: Start Condition Interrupt Enable bit

(1)

1 = Enable interrupt on detection of Start or Restart conditions

0 = Start detection interrupts are disabled

bit 4 BOEN: Buffer Overwrite Enable bit

1 = SSPBUF is updated every time a new data byte is available, ignoring the SSPOV effect on updating

the buffer

0 = SSPBUF is only updated when SSPOV is clear

bit 3 SDAHT: SDA Hold Time Selection bit

1 = Minimum of 300ns hold time on SDA after the falling edge of SCL

0 = Minimum of 100ns hold time on SDA after the falling edge of SCL

bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit

Unused in Master mode.

bit 1 AHEN: Address Hold Enable bit

Unused in Master mode.

bit 0 DHEN: Data Hold Enable bit

Unused in Master mode.

Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.