Datasheet
PIC18F97J94 FAMILY
DS30575A-page 368 2012 Microchip Technology Inc.
The SPI DMA module can write received data to all
general purpose memory on the device, including
memory used for USB endpoint buffers. The SPI DMA
module cannot be used to modify the Special Function
Registers contained in Banks 14 and 15.
20.4.5 INTERRUPTS
The SPI DMA module alters the behavior of the
SSP1IF interrupt flag. In normal non-DMA modes, the
SSP1IF is set once after every single byte is transmit-
ted/received through the MSSP1 module. When
MSSP1 is used with the SPI DMA module, the SSP1IF
interrupt flag will be set according to the user-selected
INTLVL<3:0> value specified in the DMACON2
register. The SSP1IF interrupt condition will also be
generated once the SPI DMA transaction has fully
completed and the DMAEN bit has been cleared by
hardware.
The SSP1IF flag becomes set once the DMA byte count
value indicates that the specified INTLVLx has been
reached. For example, if DMACON2<3:0> = 0101
(16 bytes remaining), the SSP1IF interrupt flag will
become set once DMABC reaches 00Fh. If user
firmware then clears the SSP1IF interrupt flag, the flag
will not be set again by the hardware until after all bytes
have been fully transmitted and the DMA transaction is
complete.
For example, if DMABC = 00Fh (implying 16 bytes are
remaining) and user firmware writes ‘1111’ to
INTLVL<3:0> (interrupt when 576 bytes are remaining),
the SSP1IF interrupt flag will immediately become set.
If user firmware clears this interrupt flag, a new inter-
rupt condition will not be generated until either: user
firmware again writes INTLVLx with an interrupt level
higher than the actual remaining level, or the DMA
transaction completes and the DMAEN bit is cleared.
Note: User firmware may modify the INTLVLx
bits while a DMA transaction is in progress
(DMAEN = 1). If an INTLVLx value is
selected which is higher than the actual
remaining number of bytes (indicated by
DMABC + 1), the SSP1IF interrupt flag
will immediately become set.
Note: If the INTLVLx bits are modified while a
DMA transaction is in progress, care
should be taken to avoid inadvertently
changing the DLYCYC<3:0> value.