Datasheet

 2012 Microchip Technology Inc. DS30575A-page 367
PIC18F97J94 FAMILY
20.4.4.3 DMABCH and DMABCL
The DMABCH and DMABCL register pair forms a
10-bit Byte Count register, which is used by the SPI
DMA module to send/receive up to 1,024 bytes for each
DMA transaction. When the DMA module is actively
running (DMAEN = 1), the DMA Byte Count register dec-
rements after each byte is transmitted/received. The
DMA transaction will halt and the DMAEN bit will be
automatically cleared by hardware after the last byte has
completed. After a DMA transaction is complete, the
DMABC register will read 0x000.
Prior to initiating a DMA transaction by setting the
DMAEN bit, user firmware should load the appropriate
value into the DMABCH/DMABCL registers. The
DMABC is a “base zero” counter, so the actual number
of bytes which will be transmitted follows in
Equation 20-1.
For example, if user firmware wants to transmit 7 bytes
in one transaction, DMABC should be loaded with
006h. Similarly, if user firmware wishes to transmit
1,024 bytes, DMABC should be loaded with 3FFh.
EQUATION 20-1: BYTES TRANSMITTED
FOR A GIVEN DMABC
20.4.4.4 TXADDRH and TXADDRL
The TXADDRH and TXADDRL registers pair together
to form a 12-bit Transmit Source Address Pointer
register. In modes that use TXADDR (Full-Duplex and
Half-Duplex Transmit), the TXADDR will be incre-
mented after each byte is transmitted. Transmitted data
bytes will be taken from the memory location pointed to
by the TXADDR register. The contents of the memory
locations pointed to by TXADDR will not be modified by
the DMA module during a transmission.
The SPI DMA module can read from, and transmit data
from, all general purpose memory on the device, includ-
ing memory used for USB endpoint buffers. The SPI
DMA module cannot be used to read from the Special
Function Registers (SFRs) contained in Banks 14
and 15.
20.4.4.5 RXADDRH and RXADDRL
The RXADDRH and RXADDRL registers pair together
to form a 12-bit Receive Destination Address Pointer.
In modes that use RXADDR (Full-Duplex and Half-
Duplex Receive), the RXADDR register will be
incremented after each byte is received. Received data
bytes will be stored at the memory location pointed to
by the RXADDR register.
Bytes
XMIT
DMABC 1+