Datasheet

 2012 Microchip Technology Inc. DS30575A-page 365
PIC18F97J94 FAMILY
20.4.4.2 DMACON2
The DMACON2 register contains control bits for
controlling interrupt generation and inter-byte delay
behavior. The INTLVL<3:0> bits are used to select
when an SSP1IF interrupt should be generated. The
function of the DLYCYC<3:0> bits depends on the SPI
operating mode (Master/Slave), as well as the
DLYINTEN setting. In SPI Master mode, the
DLYCYC<3:0> bits can be used to control how much
time the module will Idle between bytes in a transfer. By
default, the hardware requires a minimum delay of
8T
CY for FOSC/4, 9 TCY for FOSC/16 and 15 TCY for
F
OSC/64. An additional delay can be added with the
DLYCYCx bits. In SPI Slave modes, the DLYCYC<3:0>
bits may optionally be used to trigger an additional
time-out based interrupt.
REGISTER 20-5: DMACON2: DMA CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 DLYCYC<3:0>: Delay Cycle Selection bits
When DLYINTEN = 0, these bits specify the additional delay (above the base overhead of the hard-
ware), in number of T
CY cycles, before the SSP2BUF register is written again for the next transfer.
When DLYINTEN = 1, these bits specify the delay in number of TCY cycles from the latest completed
transfer before an interrupt to the CPU is invoked. In this case, the additional delay before the
SSP2BUF register is written again is 1 TCY + (base overhead of hardware).
1111 = Delay time in number of instruction cycles is 2,048 cycles
1110 = Delay time in number of instruction cycles is 1,024 cycles
1101 = Delay time in number of instruction cycles is 896 cycles
1100 = Delay time in number of instruction cycles is 768 cycles
1011 = Delay time in number of instruction cycles is 640 cycles
1010 = Delay time in number of instruction cycles is 512 cycles
1001 = Delay time in number of instruction cycles is 384 cycles
1000 = Delay time in number of instruction cycles is 256 cycles
0111 = Delay time in number of instruction cycles is 128 cycles
0110 = Delay time in number of instruction cycles is 64 cycles
0101 = Delay time in number of instruction cycles is 32 cycles
0100 = Delay time in number of instruction cycles is 16 cycles
0011 = Delay time in number of instruction cycles is 8 cycles
0010 = Delay time in number of instruction cycles is 4 cycles
0001 = Delay time in number of instruction cycles is 2 cycles
0000 = Delay time in number of instruction cycles is 1 cycle