Datasheet

PIC18F97J94 FAMILY
DS30575A-page 344  2012 Microchip Technology Inc.
19.1.2 OPEN-DRAIN OUTPUT OPTION
When operating in Output mode (the Compare or PWM
modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows
the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the
output to communicate with external circuits without the
need for additional level shifters.
The open-drain output option is controlled by the
CCPxOD bits (ODCON2<7:1>). Setting the appropri-
ate bit configures the pin for the corresponding module
for open-drain operation.
19.2 Capture Mode
In Capture mode, the CCPR4H:CCPR4L register pair
captures the 16-bit value of the Timer register selected
in the CCPTMRS1 when an event occurs on the CCP4
pin. An event is defined as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The event is selected by the mode select bits,
CCP4M<3:0> (CCP4CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP4IF (PIR4<1>),
is set. (It must be cleared in software.) If another
capture occurs before the value in CCPR4 is read, the
old captured value is overwritten by the new captured
value.
Figure 19-1 shows the Capture mode block diagram.
19.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
19.2.2 TIMER1/3/5/7 MODE SELECTION
For the available timers (1/3/5) to be used for the capture
feature, the used timers must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation will not work.
The timer to be used with each CCP module is selected
in the CCPTMRSx registers. (See Section 19.1.1 “CCP
Modules and Timer Resources”.)
Details of the timer assignments for the CCP modules
are given in Table 19-2 and Table 19-3.
Note: If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.