Datasheet
2012 Microchip Technology Inc. DS30575A-page 343
PIC18F97J94 FAMILY
19.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
19.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers, 1 through 8, that vary
with the selected mode. Various timers are available to
the CCP modules in Capture, Compare or PWM
modes, as shown in Table 19-1.
TABLE 19-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the timer to CCP enable bits in the
CCPTMRSx registers. (See Register 19-2 and
Register 19-3.) All of the modules may be active at
once and may share the same timer resource if they
are configured to operate in the same mode
(Capture/Compare or PWM) at the same time.
The CCPTMRS1 register selects the timers for CCP
modules, 7, 6, 5 and 4, and the CCPTMRS2 register
selects the timers for CCP modules, 10, 9 and 8. The
possible configurations are shown in Tab l e 1 9 -2 and
Table 19-3.
TABLE 19-2: TIMER ASSIGNMENTS FOR CCP MODULES 4, 5, 6 AND 7
TABLE 19-3: TIMER ASSIGNMENTS FOR CCP MODULES 8, 9 AND 10
CCP Mode Timer Resource
Capture
Timer1, Timer3 or Timer 5
Compare
PWM Timer2, Timer4, Timer 6 or Timer8
CCPTMRS1 Register
CCP4 CCP5 CCP6 CCP7
C4TSEL
<1:0>
Capture/
Compare
Mode
PWM
Mode
C5TSEL0
Capture/
Compare
Mode
PWM
Mode
C6TSEL0
Capture/
Compare
Mode
PWM
Mode
C7TSEL
<1:0>
Capture/
Compare
Mode
PWM
Mode
00 TMR1 TMR2 0 TMR1 TMR2 0 TMR1 TMR2 00 TMR1 TMR2
01 TMR3 TMR4 1 TMR5 TMR4 1 TMR5 TMR2 01 TMR5 TMR4
10 TMR3 TMR6 10 TMR5 TMR6
11 Reserved
(1)
11 TMR5 TMR8
Note 1: Do not use the reserved bits.
CCPTMRS2 Register
CCP8
CCP8
Devices with 32 Kbytes
CCP9 CCP10
C8TSEL
<1:0>
Capture/
Compare
Mode
PWM
Mode
C8TSEL
<1:0>
Capture/
Compare
Mode
PWM
Mode
C9TSEL0
Capture/
Compare
Mode
PWM
Mode
C10TSEL0
Capture/
Compare
Mode
PWM
Mode
00
TMR1 TMR2
00
TMR1 TMR2
0
TMR1 TMR2
0
TMR1 TMR2
01
TMR5 TMR4
01
TMR1 TMR4
1
TMR5 TMR4
1
TMR5 TMR2
10
TMR5 TMR6
10
TMR1 TMR6
11
Reserved
(1)
11
Reserved
(1)
Note 1: Do not use the reserved bits.