Datasheet

PIC18F97J94 FAMILY
DS30575A-page 336  2012 Microchip Technology Inc.
FIGURE 18-16: SIMPLIFIED STEERING
BLOCK DIAGRAM
18.4.7.1 Steering Synchronization
The STRSYNC bit of the PSTRxCON register gives the
user two choices for when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the out-
put signal at the Px<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 18-17 and 18-18 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
FIGURE 18-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
FIGURE 18-18: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
1
0
TRIS
Output Pin
(1)
PORT Data
PxA Signal
STRA
(2)
1
0
TRIS
Output Pin
(1)
PORT Data
STRB
(2)
1
0
TRIS
Output Pin
(1)
PORT Data
STRC
(2)
1
0
TRIS
Output Pin
(1)
PORT Data
STRD
(2)
Note 1: Port outputs are configured as displayed when
the CCPxCON register bits, PxM<1:0> = 00
and CCPxM<3:2> = 11.
2: Single PWM output requires setting at least
one of the STRx bits.
CCPxM1
CCPxM0
CCPxM1
CCPxM0
PWM
P1n = PWM
STRn
P1<D:A>
PORT Data
PWM Period
PORT Data
PWM
PORT Data
P1n = PWM
STRn
P1<D:A>
PORT Data