Datasheet

 2012 Microchip Technology Inc. DS30575A-page 303
PIC18F97J94 FAMILY
17.1.2 RTCVALH AND RTCVALL
REGISTER MAPPINGS
The registers described in this section are the targets
or sources for writes or reads to the RTCVALH and
RTCVALL in the order they will appear when accessed
through the RTCCON1<RTCPTR> pointer. For more
information on RTCVAL register mapping, please see
Section 17.2.8 “Register Mapping”.
REGISTER 17-5: ALRMRPT: ALARM REPEAT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
.
.
.
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to
FFh unless CHIME = 1.
REGISTER 17-6: RESERVED REGISTER (RTCVALH when RTCPTR<1:0> = 11)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 Unimplemented: Read as ‘0’
Note: A read or write to the RTCVALH register
when RTCPTR<1:0> = 11 is necessary to
automatically decrement RTCPTR.