Datasheet

 2012 Microchip Technology Inc. DS30575A-page 301
PIC18F97J94 FAMILY
Register 17-3: RTCCON2: RTC CONFIGURATION REGISTER 2
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PWCEN
(1)
PWCPOL
(1)
PWCCPRE
(1)
PWCSPRE
(1)
RTCCLKSEL1 RTCCLKSEL0 RTCSECSEL1 RTCSECSEL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PWCEN: Power Control Enable bit
(1)
1 = Power control is enabled
0 = Power control is disabled
bit 6 PWCPOL: Power Control Polarity bit
(1)
1 = Power control output is active-high
0 = Power control output is active-low
bit 5 PWCCPRE: Power Control/Stability Prescaler bits
(1)
1 = PWC stability window clock is divide-by-2 of source RTCC clock
0 = PWC stability window clock is divide-by-1 of source RTCC clock
bit 4 PWCSPRE: Power Control Sample Prescaler bits
(1)
01 = PWC sample window clock is divide-by-2 of source RTCC clock
00 = PWC sample window clock is divide-by-1 of source RTCC clock
bit 3-2 RTCCLKSEL<1:0>: RTCC Clock Select bits
Determines the source of the internal RTCC clock, which is used for all RTCC timer operations.
11 = 60 Hz Powerline
10 = 50 Hz Powerline
01 =INTOSC
00 =SOSC
bit 1-0 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bit
11 = Power control
10 = RTCC source clock is selected for the RTCC pin (pin can be LF-INTOSC or SOSC, depending on the
RTCOSC (CONFIG3L<1>) bit setting
01 = RTCC seconds clock is selected for the RTCC pin
00 = RTCC alarm pulse is selected for the RTCC pin
Note 1: The RTCCON2 register is only affected by a POR.