Datasheet

PIC18F97J94 FAMILY
DS30575A-page 290  2012 Microchip Technology Inc.
15.5.2 TIMER1/3/5 GATE SOURCE
SELECTION
The Timer1/3/5 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity
for each available source is also selectable and is
controlled by the TxGPOL bit (TxGCON <6>).
TABLE 15-2: TIMER1/3/5 GATE SOURCES
15.5.2.1 TxG Pin Gate Operation
The TxG pin is one source for Timer1/3/5 gate control. It
can be used to supply an external source to the Timerx
gate circuitry.
15.5.2.2 Timer2/4/6/8 Match Gate Operation
The TMR(x+1) register will increment until it matches the
value in the PR(x+1) register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be gener-
ated and internally supplied to the Timerx gate circuitry.
The pulse will remain high for one instruction cycle and
will return back to a low state until the next match.
Depending on TxGPOL, Timerx increments differently
when TMR(x+1) matches PR(x+1). When
TxGPOL = 1, Timerx increments for a single instruction
cycle following a TMR(x+1) match with PR(x+1). When
TxGPOL = 0, Timerx increments continuously, except
for the cycle following the match, when the gate signal
goes from low-to-high.
15.5.2.3 Comparator 1 Output Gate Operation
The output of Comparator1 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 1 with the CM1CON register, Timerx will
increment depending on the transitions of the C1OUT
(CMSTAT<0>) bit.
15.5.2.4 Comparator 2 Output Gate Operation
The output of Comparator 2 can be internally supplied
to the Timerx gate circuitry. After setting up
Comparator 2 with the CM2CON register, Timerx will
increment depending on the transitions of the C2OUT
(CMSTAT<1>) bit.
15.5.3 TIMER1/3/5 GATE TOGGLE MODE
When Timer1/3/5 Gate Toggle mode is enabled, it is pos-
sible to measure the full cycle length of a Timer1/3/5 gate
signal, as opposed to the duration of a single level pulse.
The Timerx gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. (For timing details, see Figure 15-3.)
The TxGVAL bit will indicate when the Toggled mode is
active and the timer is counting.
Timer1/3/5 Gate Toggle mode is enabled by setting the
TxGTM bit (TxGCON<5>). When the TxGTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
FIGURE 15-3: TIMER1/3/5 GATE TOGGLE MODE
TxGSS<1:0> Timerx Gate Source
00 Timerx Gate Pin
01 TMR(x+1) to Match PR(x+1)
(TMR(x+1) increments to match
PR(x+1))
10 Comparator 1 Output
(comparator logic high output)
11 Comparator 2 Output
(comparator logic high output)
TMRxGE
TxGPOL
TxGTM
TxG_IN
TxCKI
TxGVAL
Timer1/3/5
N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8