Datasheet

 2012 Microchip Technology Inc. DS30575A-page 289
PIC18F97J94 FAMILY
15.5 Timer1/3/5 Gates
Timer1/3/5 can be configured to count freely or the count
can be enabled and disabled using the Timer1/3/5 gate
circuitry. This is also referred to as the Timer1/3/5 gate
count enable.
The Timer1/3/5 gate can also be driven by multiple
selectable sources.
15.5.1 TIMER1/3/5 GATE COUNT ENABLE
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer1/3/5
will increment on the rising edge of the Timer1/3/5 clock
source. When Timerx Gate Enable mode is disabled, no
incrementing will occur and Timer1/3/5 will hold the
current count. See Figure 15-2 for timing details.
TABLE 15-1: TIMER1/3/5 GATE ENABLE
SELECTIONS
FIGURE 15-2: TIMER1/3/5 GATE COUNT ENABLE MODE
TxCLK
(†)
TxGPOL
(TxGCON<6>)
TxG Pin
Timerx
Operation
 00Counts
 01Holds Count
 10Holds Count
 11Counts
† The clock on which TMR1/3/5 is running. For
more information, see TxCLK in Figure 15-1.
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer1/3/5
N N + 1 N + 2 N + 3 N + 4